| Distance: | Job alert | Jobs 41 - 50 of 1076 |
SoC Design Engineer
Omnivision Technologies, Inc.
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Santa Clara, CA
... design flow: coding, simulation, synthesis, static timing analysis, formality verification, DFT, using Simvision, EDA tools such as Prime Time, cadence Virtuoso, Design Compiler, Integrator, and Verilog and System Verilog programming languages etc.; ... - Jun 25
Design Verification Engineer
Millennium Software and Staffing
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San Antonio, TX, 78208
looking for Design Verification Lead Engineer with following skills (verilog or UVM or OVM or soc or ARM) python (validation or verification) (arm or pcie or ddr or chi) - Jul 14
Senior Digital Design Engineer
microTECH Global Ltd
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The Netherlands
... : Developing the Register Transfer Level (RTL) design from the micro:architecture specification using Verilog or SystemVerilog as the HDL. : Developing standalone test benches to verify the RTL behavior. : Writing and verifying SystemVerilog ... - Jul 11
SoC Design Engineer
Omnivision Technologies, Inc.
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Santa Clara, CA
... design flow: coding, simulation, synthesis, static timing analysis, formality verification, DFT, using Simvision, EDA tools such as Prime Time, cadence Virtuoso, Design Compiler, Integrator, and Verilog and System Verilog programming languages etc.; ... - Jun 25
Digital Design Engineer
Apple
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Cupertino, CA
$143,100 - $214,500/yr
... 1 year experience in each of the following skills: Utilizing System Verilog or Verilog to wrote RTL for the high speed communication IPs Utilizing Scripting language (Python, Perl, or TCL), including automating the RTL integration flow, process ... - Jul 03
CAD Engineer - RTL Construction
Apple
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San Diego, CA
$171,600-$302,200/year
... Minimum requirement of Bachelors Degree +10 years of relevant industry experience Experience in programming languages such as Perl or Python Experience in Verilog/System Verilog Demonstrated experience driving large-scale software system development ... - Jul 04
CAD Engineer - RTL Construction
Apple
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Cupertino, CA
$181,100-$318,400/year
... Minimum requirement of Bachelors Degree +10 years of relevant industry experience Experience in programming languages such as Perl or Python Experience in Verilog/System Verilog Demonstrated experience driving large-scale software system development ... - Jul 04
Cellular ASIC Design Integration Engineer
Apple
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Sunnyvale, CA
$147,400-$272,100/year
... Knowledge of RTL design and HDL languages (Verilog, System Verilog, etc.) Analytical skills to be able to make design tradeoffs for best performance, low area, and low power. Experience in driving power improvements based on power analysis tools ... - Jul 06
ASIC Design Engineer - Pixel IP
Apple
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Cupertino, CA
$181,100-$318,400/year
... Experience in SoC front-end ASIC RTL digital logic design with using Verilog or System Verilog. Experience working cross-functionally with architecture, design, and verification teams to specify, design, and debug designs. Good collaboration skills ... - Jul 04
Analog Design Engineer
Jobot
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Alpharetta, GA, 30004
... Apply knowledge of SystemVerilog, PMIC, Verilog A, Virtuoso, Calibre, and Spectre in the design and development process. 3. Collaborate with cross-functional teams to define product specifications. 4. Conduct design verification and validation, ... - Jul 15