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Mid-level Cyber Research Engineer

Battelle  –  Beavercreek, OH
... Preferred Qualifications Experience with microelectronic design workflow Experience in vulnerability analysis for either software or hardware Understanding of VHDL and/or Verilog hardware description languages. Familiarity with compiled languages ... - Aug 28

FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX  –  Redmond, WA, 98052
... RESPONSIBILITIES: Design digital ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks Implement or integrate design blocks using Verilog/SystemVerilog Optimize designs for power, performance and area ... - Aug 04

CPU Core Architecture/RTL Engineer

Advanced Micro Devices , Inc.  –  Boxborough, MA, 01719
... Contribute to design verification, synthesis, power reduction, timing convergence, and floorplan efforts Preferred Experience: Verilog RTL development with industry tools in a CPU, SOC or ASIC environment Demonstrates expertise in the following: ... - Aug 04

Senior Wireless Communications Systems Engineer

eSpace  –  Saratoga, CA, 95071
... Codes Experience with hardware implementation and testing of communication systems Familiarity with software-defined radio (SDR) platforms and tools Strong programming skills in languages such as C/C++, Python, or VHDL/Verilog Master's or Ph.D. ... - Aug 08

Senior ASIC Design Verification Engineer

NVIDIA  –  Santa Clara, CA, 95053
... Proficiency with Object Oriented Programming, System Verilog, Verilog, UVM, SVA and Functional Coverage. Strong skills with VCS or equivalent simulation tools like Questa is required. Strong debugging and analytical skills are required. Have a ... - Aug 23

Lead FPGA Engineer - Electronic Warfare Design

Switch4 LLC  –  Salt Lake City, UT
... Experience leading technical employees in complex FPGA design Skilled in either VHDL (preferred) or Verilog hardware development languages. Experience implementing Electronic Support signal processing. Experience implementing Electronic Attack ... - Aug 04

FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX  –  Irvine, CA
... RESPONSIBILITIES: Design digital ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks Implement or integrate design blocks using Verilog/SystemVerilog Optimize designs for power, performance and area ... - Aug 04

Firmware Engineer

Advanced Micro Devices , Inc.  –  Rochester, NY
... knowledge of Verilog and Python is a plus Ability to adapt/learn new toolsets and frameworks is required Understanding of synchronization techniques (handshakes, message passing) ; knowledge of hardware level clocking and synchronization is a plus ... - Aug 05

Sr. ASIC Design Engineer (Silicon Engineering)

SpaceX  –  Irvine, CA
... RESPONSIBILITIES: Evaluate architectural trade-offs based on features, performance requirements and system limitations Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified ... - Aug 23

Debug Tools Engineer

Apple  –  Cupertino, CA, 95014
... Preferred Qualifications Exposure to Pre-Silicon and Emulation verification/validation Conversant with Verilog and SystemVerilog Knowledgeable in hardware architectures - SOCs, CPU, GPU, fabrics Silicon Validation Testing and Debug experience ... - Aug 22
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