| Distance: | Job alert | Jobs 271 - 280 of 1711 |
Senior ASIC Design Engineer (eInfochips Inc)
Arrow ECS
–
San Jose, CA
... Demonstrated experience in RTL coding using Verilog/System Verilog and integration of third-party IPs. A meticulous and methodical approach to triaging, debugging, and identifying root causes of issues throughout various phases of FPGA development. ... - Aug 04
SDC Engineer (eInfochips Inc)
Arrow ECS
–
San Jose, CA
... Synopsys DC/DCG/FC), Verilog/System Verilog programming Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence) Experience with Spyglass CDC and glitch ... - Aug 04
ASIC RTL/SoC Design Engineer MR Consulting
MRL Recruitment
–
Santa Clara, CA, 95053
... teamsRequired Experience & Skills: MS 5 years or PhD in Electrical Engineering with focus on RTL/SoC design Proficient in Verilog/SystemVerilog, with hands-on experience using VCS, Verdi Strong grasp of design flows, from RTL to tapeout Experience ... - Aug 04
Advanced ASIC FPGA Engineer
General Dynamics Mission Systems
–
Scottsdale, AZ, 85261
... Must be knowledgeable in VHDL and/or Verilog RTL coding and be proficient in micro-architecture design. Successful candidates will have an understanding of digital design concepts and proficient in the digital design tool flow (synthesis, timing, ... - Aug 08
FPGA Design Engineer
Compunnel
–
Indianapolis, IN, 46262
... Develop RTL using VHDL, Verilog, or SystemVerilog. Create test benches and perform simulation/debug using industry-standard tools. Achieve timing closure and optimize FPGA performance (timing constraints, synthesis, place & route, and power ... - Aug 09
Hardware/Software System Engineer (All Levels) with Security Clearance
FUSE Engineering
–
Fort Meade, MD
... * Develop and simulate HDL code (VHDL or Verilog) using ModelSim or equivalent tools. * Utilize Xilinx design tools (e.g., Vivado, ISE) for synthesis, implementation, and debugging. * Collaborate with cross-functional teams to integrate hardware and ... - Aug 16
Staff/Sr. Staff Power Analysis Engineer
Eridu AI
–
Saratoga, CA, 95071
... Knowledge of Verilog/System Verilog required. Familiarity with logic & physical design principles to drive low-power & higher-performance designs. Fluency in scripting in some of these languages: Unix, Perl, Python, and TCL Good understanding of ... - Aug 04
Digital Design Engineer - Embedded / FPGA / DSP with Security
John Galt Staffing
–
Lexington, MA, 02421
... (PL, PS, SDK, ARM, Microblaze) -- Xilinx RFSoC/MPSoC development -- VHDL / Verilog FPGA development -- Bring up and debug of FPGA based HW and FW -- Matlab / C /C++ -- Masters Degree Work from Home: This position will be approximately 40% onsite. - Aug 16
Electrical Engineer II
IntePros
–
Minneapolis, MN
... languages like C/C++ • Digital signal processing and programmable logic design • Experience with FPGA programming and VHDL/Verilog • Experience in PCB layout and grounding principles Pay & Benefits: Competitive market salary from $90,000 - $105,000 ... - Aug 08
System/Software Engineer (Chip Development) with Security Clearance
FUSE Engineering
–
Maryland
... Preferred Qualifications: Experience with Verilog and mixed-language design environments. Background in embedded systems or system-on-chip (SoC) design. Familiarity with industry-standard protocols (e.g., SPI, I2C, UART, Ethernet). Exposure to ... - Aug 16