... Preferred Qualifications: Experience with Verilog and mixed-language design environments. Background in embedded systems or system-on-chip (SoC) design. Familiarity with industry-standard protocols (e.g., SPI, I2C, UART, Ethernet). Exposure to ... - Aug 16
... Oversee the entire FPGA development lifecycle, including requirements definition, architectural design, RTL coding (VHDL/Verilog), simulation, synthesis, and on-board validation. Direct the PCB design process, from schematic capture and component ... - Aug 17
... (PL, PS, SDK, ARM, Microblaze) -- Xilinx RFSoC/MPSoC development -- VHDL / Verilog FPGA development -- Bring up and debug of FPGA based HW and FW -- Matlab / C /C++ -- Masters Degree Work from Home: This position will be approximately 40% onsite. - Aug 16
... Proficiency in programming languages such as C/C++, Verilog, Python. Strong understanding of FPGA and microprocessor architectures, peripherals, and communication protocols (e.g., UART, SPI, CANopen, EtherCAT). Experience with real-time operating ... - Aug 17
... Preferred Qualifications Solid understanding of mixed signal concepts, RTL design, Verilog and SystemVerilog Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers) Validated knowledge of synthesis, static ... - Aug 05
Advanced Micro Devices , Inc.
–
Boxborough, MA, 01719
... Experienced with Assembly, Verilog, System Verilog, C, C++. Good understanding and hands-on experience in the UVM concepts and SystemVerilog language. Good working knowledge of SystemC and TLM with some related experience. Scripting language ... - Aug 05
... failures • Develop coverage monitors and analyze coverage to ensure all test cases in the plans are covered • Develop Verilog checkers or assertions to verify the design • Work with the silicon bringup team on developing tests that help the ... - Aug 04
... Knowledge of basic SoC Architecture and HDL languages like Verilog / System Verilog to collaborate with our logic design team for timing fixes and functional ECOs. Preferred Qualifications Hands-on experience in timing/SDC constraints generation, ... - Aug 04
... Preferred Qualifications: Experience with VHDL and Verilog languages. Experience with debugging (GDB, WinDBG, Visual Studio, etc.). Experience with statistical analysis of entropy sources. Knowledge of OpenSSL and/or OpenPGP. Vulnerability analysis ... - Aug 04