| Job alert | Jobs 51 - 60 of 67 |
Senior Digital Design Engineer
Mulya Technologies
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Bengaluru, Karnataka, India
... STA/lint/LEC/…) FPGA build up and verification What we expect to see: BS, MS or PhD in electrical engineering, computer engineering or computer science with a special focus on digital system design, computer architecture or computer hardware design. ... - Jun 18
Principal Engineer, Physical Design
Analogdevices
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Sadduguntepalya, Karnataka, 560029, India
... STA Lead, responsible for constraints generation, STA setup, analysis and ECO generation who has sound working knowledge in PT/tempus STA setup environment with low power aware implementation methodology knowhow. For positions requiring access to ... - May 29
SOC Design Engineer
Intel
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Sadduguntepalya, Karnataka, 560029, India
... - Experience with synthesis, DFT, FV, and STA. - Familiarity with protocols like AHB, AXI, ACE, and CHI is desirable. - Hands-on experience in multi-clock designs and asynchronous interfaces. - Ability to define microarchitecture specifications and ... - Jun 05
SOC Design Engineer
Intel
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Sadduguntepalya, Karnataka, 560029, India
... - Experience with synthesis, DFT, FV, and STA. - Familiarity with protocols like AHB, AXI, ACE, and CHI is desirable. - Hands-on experience in multi-clock designs and asynchronous interfaces. - Advanced knowledge of low-power techniques and tools ... - Jun 05
Processor Subsystem Architect
Intel
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Sadduguntepalya, Karnataka, 560029, India
... and RTOS Must have working experience on DFT (scan, mbist), DFD (debug/trace), synthesis/STA Must be able to review microarchitecture, RTL, CDC/RDC/Lint reports, performance/timing/power reports and debug, resolve issues in execution very quickly. ... - May 28
Applications Engineering, Sr Engineer
Synopsys
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Sadduguntepalya, Karnataka, 560029, India
... PrimeLib’s innovative technologies utilize embedded gold reference SPICE engines to provide a characterization speed up of advanced Liberty™ models used by PrimeTime static timing analysis (STA) to accurately account for effects seen in ultra-low ... - Jun 14
Physical Design Lead Engineer - RTL/GDSII
MY Search
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Koramangala, Karnataka, 560034, India
... - Must have in-depth knowledge of entire physical design process from RTL to GDSII generation which includes Floorplan, Placement, CTS, Routing and Sign Off (STA, PV, IR/EM) - Must have hands on experience in 7nm - Must have exposure to 2.5 GHz ... - Jun 20
VLSI Technical SOC/TOP Level Design and Integration Engineer
Broadcom
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Electronic City, Karnataka, 560100, India
... Top-Level integration flows ( integrating multiple IPs and associated, clock domains ) Synthesis ( DC ) and Timing Concepts (STA) Spyglass ( lint, DFT, PM, CLK/RST, CDC) Formal Verification, Conformal LEC) Perl scripting CAD Tools : Cadence/Synopsys ... - Jun 19
DFT Lead - IP & SoC Design - ATPG/MBIST/Cadence Tool
MY Search
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Bengaluru, Karnataka, India
... nodes - Hands-on experience with industry Standard tools like Cadence, Synopsys or Mentor - Exposure to STA tool, timing closure & ECO implementation for DFT modes is a great plus - Prior experience with post-silicon debug is an added advantage. ... - Jun 20
DFT Engineer - RTL/Shell Scripting - VLSI Domain
MY Search
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Bengaluru, Karnataka, India
... - Work with STA engineer to define timing constraints for DfT modes - Support Test engineer in silicon debug and pattern delivery for ATE - Experience in RTL coding, shell scripting - Experienced in handling analog DFT simulations - Be fluent with ... - Jun 20