| Job alert | Jobs 21 - 30 of 67 |
Principal Design Engineer(DFT)
Cadence Design Systems
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Bengaluru, Karnataka, India
... · Exposure to RTL2GDS flow and tasks such as synthesis and scan insertion, STA and IR drop. · Good understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis are plus. · ... - Jun 15
Physical Design Engineer
Tech Mahindra
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Bengaluru, Karnataka, India
... Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Well versed of Unix command and system. Strong ... - Jun 18
Physical Design Engineer
BITSILICA
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Bengaluru, Karnataka, India
... Should have a strong understanding of STA Concepts and Handle the Timing ECOs. Must have Hands on experince on DRC/LVS Closure - May 26
DFT Engineer
Tech Mahindra
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Bengaluru, Karnataka, India
... design rules, quality and guidelines are met, and to ensure maximum Test Coverage · Work closely with Physical Design and STA teams to ensure correct DFT-Implementation and DFT-Timing Closure · Collaborate with post-silicon and manufacturing team ... - Jun 18
Senior SOC Physical Design Engineers
Samsung Semiconductor
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Bengaluru, Karnataka, India
... Complex SOC Top Physical Implementation for next generation SoCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis, Place and Route, STA, timing and physical signoffs - Hands on experience doing ... - Jun 18
Physical Design Engineer
Wafer Space - An ACL Digital Company
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Bengaluru, Karnataka, India
... stages of the design (floor planning, placement, CTS, routing, physical verification, IREM) • Well versed with the timing closure (STA), timing closure methodologies • Good Understanding of DRC, LVS,ERC and PERC rule files for lower tech node layout ... - May 31
Physical Design Engineer
Wafer Space - An ACL Digital Company
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Bengaluru, Karnataka, India
... ● Well versed with the timing closure (STA), timing closure methodologies. ● Good Understanding of DRC, LVS,ERC and PERC rule files for lower tech node layout verification. ● Experience in lower tech nodes (<7nm). ● Good automation skills in PERL, ... - Jun 05
Lead Physical Design Engineer
eInfochips (An Arrow Company)
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Bengaluru, Karnataka, India
... Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints. Good exposure to ICC2/Innovus/Calibre/Formality/LEC tool set. Well versed in automation skills using shell/tcl/perl/python - Jun 20
Senior Staff DFT Engineer
Marvell
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Bengaluru, Karnataka, India
... Insertion, verification on RTL/Netlist level Cross domain knowledge to resolve DFT issues with design, synthesis, Physical design, STA team Good knowledge on Perl/ Tcl scripting Proven experience on gate level simulations with notiming and SDF based ... - Jun 20
Senior Staff Engineer, Physical Design
Marvell
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Bengaluru, Karnataka, India
... #LI-MN1 What We're Looking For Bachelor or Master degree in Electronics Engineering Minimum 6 years experience with industry-standard Physical Design implementation tools Excellent skills in Backend flow – Synthesis, P&R, physical verification, STA ... - Jun 10