| Job alert | Jobs 1 - 10 of 171 |
ASIC Verification Engineer- UVM / RISC-V / System Verilog
European Recruitment
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San Jose, CA
ASIC Verification Engineer- UVM / RISC-V / System Verilog We are partnered up with a well-established Semiconductor organisation who enable state of the art perception for autonomous vehicles who are looking for Senior ASIC Verification Engineer to ... - May 19
Design Verification Engineer PCIe/HBM
Mirafra Technologies
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San Jose, CA
... Strong coding skills in Verilog/System Verilog, C/C++, Scripting languages like Perl/Python is a MUST, and System Verilog and UVM programming experience is a MUST. Strong analytical problem solving, and attention to detail. - May 17
Compiler Engineer
Efficient Computer
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Santa Clara, CA, 95053
... Experience with verilog, system verilog, or VHDL. Knowledge of computer architecture. About Efficient Corporation: Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses ... - May 04
Senior Design Verification Engineer
Mirafra Technologies
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San Jose, CA
... Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for ... - May 13
RTL Design Engineer
LanceSoft, Inc.
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San Jose, CA
JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for ... - May 09
SOC Architect
Mumba Technologies, Inc.
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San Jose, CA
... Familiarity with Verilog RTL and programming languages. Experience with compute intensive hardware and ability to work with algorithm groups to translate algorithm specifications into hardware. Familiarity with AI algorithms is a plus. - May 11
Senior HAPS Validation Engineer
Mirafra Technologies
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San Jose, CA
... Qualifications Knowledge of RTL logic design (Verilog), strong experience working with FPGAs. Familiarity with PCIe, USB, Ethernet, ARM, and other commonly used blocks in SoC designs; Strong experience working with FPGA tools like Vivaldo Familarity ... - May 23
Senior Design Verification Engineer
Canvendor
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San Jose, CA
... • Proficient in System Verilog/UVM/OVM, OOP/C++ • Knowledge of GPU, experience with Shader, Texture, or Memory System a plus • Experience with code coverage and functional coverage driven verification methodology. • Experience in creating, running ... - May 13
System on a Chip Architect
Mumba Technologies, Inc.
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San Jose, CA
... • Familiarity with Verilog RTL and programming languages. • Experience with compute intensive hardware and ability to work with algorithm groups to translate algorithm specifications into hardware. • Familiarity with AI algorithms is a plus - May 17
Design Verification Engineer
Intelliswift Software
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San Jose, CA
Design Verification Engineer - Remote / San Jose, CA Duration – 6 months + (can be extended longer) San Jose, CA / Remote Design Verification Engineer UVM System Verilog Test Bench Development SystemC (preferred) strong C/C++ - Apr 26