| Job alert | Jobs 61 - 70 of 174 |
Senior Design Verification Engineer
Intuitive
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Sunnyvale, CA
... or equivalent experience Advanced knowledge of HVL methodology (UVM) Experience with OOP constructs Expertise in HVL and HDL (SystemVerilog, Verilog) Experience defining coverage space and writing coverage model Experience with SystemVerilog ... - Jun 05
System and Chip Simulation Engineer
Enfabrica
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Mountain View, CA, 94043
... proficiency in Verilog/SystemVerilog and testbench creation a plus. Powered by JazzHR 5zcNm3C5KS - Jun 10
RTL Design Engineer
Quest Global
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Mountain View, CA, 94039
... Experience with RTL coding using Verilog/VHDL/System Verilog. Experience in micro-architecture & designing cores and ASICs. Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc. Exposure in scripting (Pearl/Python/TCL ... - Jun 02
Senior Staff Digital Verification Engineer
Alpha & Omega Semiconductor
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Sunnyvale, CA, 94085
... test writing and verification of several products Experience with using the Cadence Virtuoso software and AMS simulation environment Comfortable with exploring the analog schematic hierarchy in Cadence Able to write and debug System Verilog models. ... - Jun 03
Sr. DFT Engineer
Ambarella Corp
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Santa Clara, CA
$115,000 - $150,000
... Minimum Requirements: MS in Electrical / Computer Engineering or BS in Electrical/Computer Engineering with 1-5yrs of experience in DFT implementation Knowledge of DFT fundamentals Knowledge of Logic design and timing Knowledge of Verilog, Perl & ... - Jun 14
Integrated Circuit Design Engineer
Unreal Gigs
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San Jose, CA
... Strong understanding of digital design, RTL synthesis, Verilog AMS, SystemVerilog, and familiarity with analog circuit blocks and device physics. Benefits Competitive salary with potential for bonuses based on performance. Comprehensive benefits ... - Jun 06
Physical Design Engineer Intern
Ambarella Corp
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Santa Clara, CA
... Hardware Design Languages like Verilog, VHDL Self-motivated team worker, good verbal and written communication skills. Experience with Cadence Encounter/RTL compiler/Conformal/QRC would be an added advantage. Solid understanding of hierarchical ... - Jun 14
Systems Design Architect
Cadence Design Systems
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San Jose, CA, 95123
... Expertise in Verilog/System Verilog for coding and verification. Proficiency in RTL design techniques, including synthesis, timing closure, and verification. Experience in using UVM for functional verification of ASIC designs. Experience with EDA ... - Jun 11
Design Engineer MM
Young Stealth Company
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Fremont, CA
... budget regarding data path deep understanding redundancy control scheme need to closely working with layout engineers Verilog verification expertise- required HBM expertise- required Rx/Tx/ODT/ZQ cal/ESD -required Additional Plus to Application: ... - Jun 08
Senior Digital Design Engineer
Ethan Alexander Group
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Santa Clara, CA
... Requirement Document (PRD) Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL Developing standalone testbenches to verify the RTL behavior Writing and verifying ... - Jun 10