| Job alert | Jobs 51 - 60 of 174 |
Mixed Signal Engineer
Ambarella Corp
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Santa Clara, CA
... For Digital oriented: • Good knowledge of digital front-end design, including Verilog coding and timing analysis • Familiar with analog integrated circuit and mixed signal verification • Knowledge of digital back-end flow is a plus For Analog ... - Jun 14
Design Engineer MM
Young Stealth Company
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Fremont, CA
... GDDRx, HBM, Serial Link] Understanding Memory Core operation understanding IBIS model *** understanding DLL/PLL/DCC is a Verilog verification expertise required PLUS HBM expertise required Scripting language experience required E04JI80240jb4030y0e - Jun 08
Senior Engineer, CPU Architecture
Samsung Semiconductor
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San Jose, CA
... Strong background in computer architecture Experienced with hardware languages like Verilog, SystemVerilog, SystemC, Chisel. Experience in architectural modeling & performance/cost analysis. Good knowledge in ASIC design flow. Excellent ... - Jun 08
Senior Engineering Manager
Cadence Design Systems
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San Jose, CA
... Substantial experience with Verilog is required, as are excellent logic and debug skills. Engineering expertise in mixed-signal IP development procedures and Ethernet connectivity protocol knowledge are also strongly preferred. #J-18808-Ljbffr - Jun 16
System-on-Chip Design Engineer
Greenlight Professional Services
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Santa Clara, CA, 95054
... Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools. Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM. Experience generating test vectors ... - May 28
Senior Static Timing Analysis (STA) Engineer
Chelsea Search Group
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San Jose, CA, 95113
... in Timing closure, Physical Design, Floor-planning, and Place & Route • Knowledge of basic Architecture and Verilog to collaborate with RTL and IP design teams for timing fixes • Contribute to timing flow and methodology improvements • BSEE required - Jun 12
Hardware Emulation Engineer
Enfabrica
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Mountain View, CA, 94043
... Good understanding of Verilog and SystemVerilog RTL design. Exposure to synthesizable SystemVerilog/Verilog code and SVAs. Strong communication skills and a team player. MS with 5+ years of experience, BS with 7+ years experience. Preferred ... - Jun 06
Hardware Infrastructure Development Engineer
VeeAR Projects Inc.
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Sunnyvale, CA, 94087
... Hardware Modeling: Familiarity with hardware modeling concepts, including the ability to work with hardware description languages (e.g., Verilog), is a plus. Understanding the intricacies of hardware design and modeling will be beneficial in this ... - May 26
Design Verification Engineer
Etched.ai
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Cupertino, CA
... Help develop a post-silicon validation and bring up strategy You may be a good fit if you: Have a deep knowledge of Verilog and UVM Have a bachelor’s degree or equivalent experience in electrical engineering, computer science, physics, or ... - May 29
RTL Design Engineer - Senior (US)
Managed Staffing
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Santa Clara, CA, 95054
... PREFERRED EXPERIENCE: • 10 years' experience in RTL coding • Knowledge of PCIe Gen5 and PIPE specification • Knowledge of ASIC development flows • Knowledge of system verilog • Multi-clock domain designs. • Design constraints for synthesis and ... - May 22