| Job alert | Jobs 41 - 50 of 224 |
Sr. FPGA Design Engineer (Contract)
USA Tech Recruitment
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San Jose, CA
... Strong Verilog HDL programming skills, with experience targeting RTL designed for custom ASIC Development to a Xilinx FPGA. Experience designing solutions that interface with Ethernet based protocols, PCIe, and optical transceivers, with knowledge ... - Jun 18
DFT Engineer
ACL Digital
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San Jose, CA
... Hands-on experience with Verilog behavioral RTL and Gate level net list. Generating, verifying, and debugging test patterns to test the designs and firmware for new FPGA families. Improving, extending, and porting existing manufacturing test designs ... - Jun 02
Integrated Circuit Design Engineer
Unreal Gigs
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San Jose, CA
... Experience: Minimum 8+ years of experience in IC Design with a solid understanding of analog and digital design, Verilog, and familiarity with device physics. Benefits Competitive salary with potential for bonuses based on performance. Comprehensive ... - Jun 22
Senior Design Verification Engineer
Canvendor
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San Jose, CA
... • Proficient in System Verilog/UVM/OVM, OOP/C++ • Knowledge of GPU, experience with Shader, Texture, or Memory System a plus • Experience with code coverage and functional coverage driven verification methodology. • Experience in creating, running ... - Jun 18
ASIC/RTL/SOC Design Engineer
Wipro
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Sunnyvale, CA, 94087
... Expertise in Verilog & System Verilog is a must. Experience in Synthesis / Understanding of timing concepts for ASIC is required. Static checking tools like Lint, CDC, RDC, Spyglass DFT etc experience required. Experience in design of DDR / USB ... - Jun 20
ASIC Design Engineer
Ambarella Corp
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Santa Clara, CA
$135,000 - $150,000
... Designing and implementing video compression logic, image processing logic, and computer vision processors in Verilog and SystemVerilog. Design integration, logic synthesize, and design optimization for timing, area and power. Developing unit level ... - Jun 14
Design for Test (DFT) Engineer
ATR International
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Milpitas, CA, 95035
... Strong knowledge of DFT methodologies, industrial standards, and practices Strong working knowledge of Chip design, Verilog/System Verilog, and design verification Experience with STA tools like Primetime, SDF generation and Gate-level simulations ... - Jun 18
ASIC Engineer
Juniper Networks
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Sunnyvale, CA
... Develop block level verification environment using Universal Verification Methodology (UVM) and System Verilog. Part-time tel... - Jun 18
Field-Programmable Gate Arrays Engineer
Wipro
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San Jose, CA
... Strong Verilog HDL programming skills, with experience targeting RTL designed for custom ASIC Development to a Xilinx FPGA. Experience designing solutions that interface with Ethernet based protocols, PCIe, and optical transceivers, with knowledge ... - Jun 21
Hardware Design Engineer
Sedaa Corp
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San Jose, CA
... Desired Qualifications: Verilog Perl Scripting CAD Tools Job title - Hardware Engineering Failure Analysis Location - San Jose, CA (onsite) The position requires the candidate to have had HW design experience so that they can troubleshoot issues ... - Jun 18