| Job alert | Jobs 31 - 40 of 226 |
RTL Design Engineer
LanceSoft, Inc.
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San Jose, CA
... PREFERRED EXPERIENCE: • 10 years' experience in RTL coding • Knowledge of PCIe Gen5 and PIPE specification • Knowledge of ASIC development flows • Knowledge of system verilog • Multi-clock domain designs. • Design constraints for synthesis and ... - May 26
Design Engineer V (Power engineering, Silicon Power Characterization
Aditi Consulting
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Sunnyvale, CA
... Primary languages are Python, TCL and System Verilog. Responsibilities: Perform PPA optimization with Fusion compiler. Perform RTL and netlist level Power analysis Perform post-processing and scripting on report log files for format conversion, data ... - Jun 19
ASIC Design Verification Engineer
Acceler8 Talent
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San Jose, CA
... As a Design Verification Engineer with this company you will work with test bench development using System Verilog and UVM as well as develop comprehensive test plans and cases with functional coverage, assertions, and coverage properties. You will ... - Jun 18
RTL Design Engineer
Sapear Inc
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Mountain View, CA
... Proficient in Verilog/System Verilog coding constructs. Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) Experience with high speed PCIe designs and protocols. Experience with ... - Jun 20
Field-Programmable Gate Arrays Engineer
Wipro
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San Jose, CA
... Strong Verilog HDL programming skills, with experience targeting RTL designed for custom ASIC Development to a Xilinx FPGA. Experience designing solutions that interface with Ethernet based protocols, PCIe, and optical transceivers, with knowledge ... - Jun 21
VLSI Verification Engineer
Intellectt INC
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San Jose, CA
... Proficiency in verification tools and languages such as SystemVerilog, UVM, and Verilog. Experience with linting, CDC analysis, RDC analysis, and constraints verification. Familiarity with industry-standard protocols such as HBI, HBM, UCIe, PCIe, ... - Jun 17
Design Engineer V (Power engineering, Silicon Power Characterization
Aditi Consulting
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Sunnyvale, CA
... Primary languages are Python, TCL and System Verilog. Responsibilities: Perform PPA optimization with Fusion com... - Jun 20
Firmware Engineer
Etched.ai
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Cupertino, CA
... oscilloscopes) Desired Qualifications: Experience working in hardware simulation/emulation environments Experience with HBM, PCIe, or Ethernet SERDES Familiarity with Verilog language How we’re different: Etched believes in the Bitter Lesson. We ... - Jun 15
FPGA Verification Engineer
Arista Networks
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Santa Clara, CA
... Create and maintain test benches in Verilog/SystemVerilog Create BFM, RTL models for new and existing designs Develop the verification test plans and test cases Review the design functional coverage Concepts and Skills: Work with Data and control ... - Jun 20
Design Verification Engineer
Expedite Technology Solutions, LLC
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Santa Clara, CA, 95054
Responsibilities: • Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. • Develop test plans and coverage metrics from ... - Jun 21