| Job alert | Jobs 21 - 30 of 223 |
Field Application Engineer
Linkconn Electronics U.S. Inc.
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Santa Clara, CA, 95054
... Education or experience must include: Linear Systems, Microprocessors, Verilog, and Digital Systems. Any suitable combination of experience, education, or training is acceptable. To apply, mail resumes in attention to: HR, 4701 Patrick Henry Drive, ... - Jun 18
Design Engineer V (Power engineering, Silicon Power Characterization
Aditi Consulting
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Sunnyvale, CA, 94087
... Primary languages are Python, TCL and System Verilog. Responsibilities: Perform PPA optimization with Fusion compiler. Perform RTL and netlist level Power analysis Perform post-processing and scripting on report log files for format conversion, data ... - Jun 19
Application Specific Integrated Circuit Verification Engineer
Wipro
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San Jose, CA
7+ years of ASIC verification experience with UVM (or similar methodology/tools) and excellent Verilog/System Verilog programming skills - must have previously worked on an engineering team that has taped out & successfully shipped at least one high ... - Jun 18
Senior Electrical Engineer
Intelliswift Software, Inc
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Sunnyvale, CA, 94087
... Must have for FPGA: need to know how to code Verilog. Good to have skills: PCB board design and bring up Electrical Engineering design verification and validation Electrical Engineering single simulation capability - May 26
RTL Design Engineer
Sapear Inc
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Mountain View, CA, 94043
... Proficient in Verilog/System Verilog coding constructs. Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) Experience with high speed PCIe designs and protocols. Experience with ... - Jun 21
Lead ASIC Verification Engineer
Lumotive
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San Jose, CA
... Strong knowledge in ARM based SOC verification, building System Verilog and Verilog-A Model for complex Analog Subsystem. Experience in building Verilog and Verilog A model for Analog components. Experience with SystemVerilog, UVM and AMS ... - Jun 08
Design Verification Engineer
SilverSpace Technologies Inc
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San Jose, CA
Job Title: Design Verification Engineer Qualification Required: Typically requires minimum of 5-15 years of experience in System Verilog, UVM. Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering. ... - Jun 22
Design Engineer V (Power engineering, Silicon Power Characterization
Aditi Consulting
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Sunnyvale, CA, 94087
... Primary languages are Python, TCL and System Verilog. Responsibilities: Perform PPA optimization with Fusion compiler. Perform RTL and netlist level Power analysis Perform post-processing and scripting on report log files for format conversion, data ... - Jun 19
RTL Design Engineer - AXI, Lint and CDC San Jose, CA - Onsite
Infobahn SoftWorld Inc
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Santa Clara, CA
Role Title: RTL Design Engineer Location: San Jose, CA Duration: 12+ months contract TOP SKILLS: ASIC Design RTL Design/Integration System Verilog AXI Design quality checks such as CDC and Lint JOB DUTIES: Responsible for RTL design using Verilog ... - Jun 21
Design Verification Engineer
Acceler8 Talent
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San Jose, CA
... Requirements: 5+ years of hands-on experience in ASIC DV Experience with UVM or System Verilog B.S. (M.S. preferred) degree in Electrical or Computer Engineering - Jun 17