| Job alert | Jobs 11 - 14 of 14 |
ASIC Digital Design, Staff Engineer
Synopsys
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Hadapsar, Maharashtra, 411028, India
... May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) Identify design problems, ... - May 15
Design Eng 4 - LPQ
Lattice Semiconductor Corp.
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Shivaji Nagar, Maharashtra, 411016, India
... TL development with Verilog-HDL. Good understanding of mapping ML operations to logic. Low power design techniques. RISC-V based system extension. Education and General BS/MS/PhD in Electronics or Computer Engineering minimum of 8 years (6 years for ... - May 22
Design Eng 4 - LPQ
Lattice Semiconductor Corp.
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Shivaji Nagar, Maharashtra, 411016, India
... Advanced knowledge of System Verilog and UVM methodology. Experience in using programming languages such as C/C++, Perl/Python/Tcl for automatic the DV tasks. Hands-on verification experience in verifying IPs using AMBA bus architecture in UVM ... - May 16
Analog Design, Staff Engineer
Synopsys
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Tingre Nagar, Maharashtra, 411015, India
... Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture. Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desired. Good communication and documentation skills. Business Title (Title ... - May 21