| Job alert | Jobs 1 - 9 of 9 |
Software Defined Radio Engineer
Raphe mPhibr
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Noida, Uttar Pradesh, India
... Designing in-house IP blocks for our core payload in a hardware description language (verilog, VHDL). Developing test software and drivers to support unit, integration, and system testing of all SDR software functions. Updating or creating linux ... - Jun 18
Senior Verification Engineer
NXP Semiconductors
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Noida, Uttar Pradesh, India
... · Fluency in design & verification languages such as VHDL, Verilog, C and System Verilog. · Skilled in EDA test regression tools associated to Digital Front End Flow as vManager cadence tools. · Exposure to Low-power design and UPF methodology. · ... - Jun 16
Hardware Design Developer - System Verilog
Swift Placements
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Lodhi Estate, Delhi, 110003, India
... - Expertise in HDLs such as Verilog, SystemVerilog, VHDL, and SystemC. (ref:hirist.tech) - Jun 20
Details
NTT DATA Inc
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Ansari Nagar East, Delhi, 110029, India
Not Specified
... FPGA programming in VHDL or Verilog Participate in preparation and execution of Module projects running in R&D with competence in. designing of C/C++ embedded software and Python. Publish design guides, Requirement specification documents Follow ... - Jun 01
R&D Engineering, Sr Staff Engineer
Synopsys
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Sector 25A, Uttar Pradesh, 201301, India
... The person should have experience in C++, Verilog/VHDL and scripting. Problem solving and debugging for issues is key responsibility of the job. Customer interfacing and helping CAE with customer issues is required. Fast learner and effective ... - Jun 18
ASIC Digital Design, Staff Engineer
Synopsys
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Sector 55, Uttar Pradesh, 201307, India
... written and spoken English communication skills Demonstrate good review and problem-solving skills Knowledgeable with Verilog, VHDL and/or SystemVerilog Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus Understanding of ... - May 25
R&D Engineering, Staff Engineer
Synopsys
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Sector 25A, Uttar Pradesh, 201301, India
... Good knowledge of Verilog, SystemVerilog & VHDL HDL. Familiarity with ASIC design flow and the EDA tools and methodologies used therein. Familiarity with multi-threaded and distributed code development. Self-motivation, self- discipline and the ... - Jun 21
Applications Engineering, Sr Engineer
Synopsys
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Sector 25A, Uttar Pradesh, 201301, India
... Strong HDL language support (Verilog, VHDL, System Verilog) Digital design fundamental and RTL coding understanding Good Debugging skills. Scripting – Perl, TCL, Make, Shell Scripting. Role - Static Product Engineer Solid fundamentals in Digital ... - Jun 07
Applications Engineering, Staff Engineer
Synopsys
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Sector 55, Uttar Pradesh, 201307, India
... The Engineer will also design and develop tests in VHDL/Verilog/System Verilog languages, resolving compile and functional/runtime issues for the zebu emulation platform. The candidate will benchmark various performance and compile time metrices of ... - Jun 18