| Job alert | Jobs 1 - 8 of 8 |
RTL Designer - ASIC Tools
Apolis India
–
Lodhi Estate, Delhi, 110003, India
... System-level Validation in FPGA, ASIC, CPU or custom IC designs. 10. Strong self-initiative and persistence with the ability to deal with ambiguity to focus and achieve end goals. 11. The candidate must have a high focus on discipline in execution, ... - Jun 20
SoC Verification Engr
NXP Semiconductors
–
Noida, Uttar Pradesh, India
... • Define and code test cases and debug these on the design models (RTL, Power aware RTL, Gate Level, FPGA) and on silicon. • Define goals for the verification coverage, implement appropriate methods to measure the verification coverage, and enhance ... - May 29
Software Defined Radio Engineer
Raphe mPhibr
–
Noida, Uttar Pradesh, India
... Hands-on experience in FPGA programming and customization. Well-versed with testing and validating hardware blocks in both simulations and on target. Designing in-house IP blocks for our core payload in a hardware description language (verilog, VHDL ... - Jun 18
Details
NTT DATA Inc
–
Ansari Nagar East, Delhi, 110029, India
Not Specified
... During development collaborates with other specialists (EE, FPGA Engineers, SW, etc.). This embedded software controls electronics for focused ion chromatography systems. These products are sophisticated electro-mechanical systems that include ... - Jun 01
R&D Engineer (C/C++, Unix, DS, Algorithm with 3-8 years of exp)
Synopsys Inc
–
Noida, Uttar Pradesh, India
and Requirements : The position is for a Staff software engineer in the FPGA Synthesis and prototyping team at Synopsys. The ProtoCompiler and Synplify synthesis products deliver superior quality of results (QoR), turnaround time, hierarchical flows ... - May 30
R&D Engineering, Architect
Synopsys
–
Sector 25A, Uttar Pradesh, 201301, India
... time candidate to work on the industry's leading and fastest emulation system, Zebu Server, which offers the industry's largest design capacity, supporting SOC chips as large as 10 billion gates based on high-density 20 nano-meter FPGA technology. ... - Jun 18
Applications Engineering, Staff Engineer
Synopsys
–
Sector 55, Uttar Pradesh, 201307, India
... In addition, this is a great opportunity to work with a wide suite of in-house digital design and verification tools, including VCS, Verdi as well as Xilinx FPGA Vivado tool. Role would also provide opportunity to verify and create debug solutions ... - Jun 18
Analog Layout Design Lead - Cadence Tool
MY Search
–
Ganesh Nagar, Delhi, 110092, India
... Our client's cutting edge solutions include : - ASIC Design - Verification - Physical Design - DFT - Circuit Design & Layout - FPGA Design and Emulation They are looking for Analog Layout Design Lead to be based at Noida with the following: - Total ... - Jun 20