| Job alert | Jobs 11 - 14 of 14 |
Lead Engineer (IP Design & Digital Signal Processing)
Siemens EDA (Siemens Digital Industries Software)
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Noida, Uttar Pradesh, India
... criteria’s for the IP in high level design and verification environment Author detailed design documents QUALIFICATIONS: 5 -11 years of RTL design experience (Verilog, SystemVerilog, digital microarchitecture) BS plus 8 years relevant experience. ... - Sep 23
Test & Validation Engineering, Sr Engineer
Synopsys
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Sector 25A, Uttar Pradesh, 201301, India
... Synopsys EDA tools (SpyGlass, VC SpyGlass, VCS, Verdi) would be added advantage Solid fundamentals in Digital design, HDLs (Verilog/VHDL) and System Verilog Excellent written and oral communication skills is a must as the role requires interfacing ... - Sep 06
R&D Engineering, Sr Staff Engineer
Synopsys
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Sector 25A, Uttar Pradesh, 201301, India
... 7+ years’ experience in developing HVL based verification environments, preferably using System Verilog. Exposure to coverage driven verification. Experience in verification methodologies like UVM/OVM. Exposure to complex SV test benches involving ... - Sep 08
Analog Design, Staff Engineer
Synopsys
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Sector 25A, Uttar Pradesh, 201301, India
... including PCIe, 10G/25G/56G/112G Ethernet, JESD204C, CPRI Experience with lab tests for high-speed serial links Experience with C/Verilog-A/systemVerilog Our Silicon IP business is all about integrating more capabilities into an SoC—faster. ... - Sep 06