| Job alert | Jobs 21 - 27 of 27 |
Applications Engineering, Staff Engineer
Synopsys
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Sector 55, Uttar Pradesh, 201307, India
... The Engineer will also design and develop tests in VHDL/Verilog/System Verilog languages, resolving compile and functional/runtime issues for the zebu emulation platform. The candidate will benchmark various performance and compile time metrices of ... - Jun 18
Applications Engineering, Sr Staff Engineer
Synopsys
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Sector 55, Uttar Pradesh, 201307, India
... (HPC, mobile, storage, automotive, networking, IoT), from IP requirements perspective Hands-on experience of RTL coding in Verilog, simulation, synthesis, static timing analysis, equivalence checking Domain knowledge of embedded memories, logic ... - May 24
ASIC Digital Design, Staff Engineer
Synopsys
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Sector 25A, Uttar Pradesh, 201301, India
... Shell/Python/Tcl- Knowledge of High Speed Serdes Protocols/RTL is an advantage What the candidate will do Implement RTL in Verilog and run Spyglass CDC/RDC/Lint/ Tmax Work on Synthesis constraints Work on digital design flows Experience : 3+ year ... - Jun 19
ASIC Digital Design, Staff Engineer
Synopsys
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Sector 55, Uttar Pradesh, 201307, India
... - Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. - Exposure to IP design and verification processes including VIP development is an added advantage. - Basic understanding of functional & Code coverage. ... - May 25
ASIC Digital Design, Staff Engineer
Synopsys
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Sector 55, Uttar Pradesh, 201307, India
... You will own RTL architecture design, micro architecture design, clock partitioning, RTL realization in System Verilog, Design Flow Clean up, Product documentation and Release As part of the work, you will closely work with and lead and mentor a ... - Jun 03
ASIC Digital Design, Staff Engineer
Synopsys
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Noida, Uttar Pradesh, India
... Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI,APB,AHB) etc Good knowledge of System Verilog. Hands-on experience with coverage closure and writing SVA for IP/SOC. Good simulation debugging skills. Experience with ... - Jun 12
ASIC Digital Design, Sr Staff Engineer
Synopsys
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Noida, Uttar Pradesh, India
... Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI,APB,AHB) etc Good knowledge of System Verilog. Hands-on experience with coverage closure and writing SVA for IP/SOC. Good simulation debugging skills. Experience with ... - Jun 12