| Job alert | Jobs 11 - 20 of 27 |
ASIC Digital Design, Staff Engineer
Synopsys
–
Sector 55, Uttar Pradesh, 201307, India
... May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) Identify design problems, ... - May 25
R&D Engineering, Staff Engineer
Synopsys
–
Sector 25A, Uttar Pradesh, 201301, India
... Languages: Hands-on experience with System Verilog & Verilog. Should have good knowledge of Object-Oriented Programming(UVM). Languages: Python, TCL, or shell Scripting is plus. Job responsibilities Able to individually contribute to the development ... - Jun 21
Details
NTT DATA Inc
–
Ansari Nagar East, Delhi, 110029, India
Not Specified
... FPGA programming in VHDL or Verilog Participate in preparation and execution of Module projects running in R&D with competence in. designing of C/C++ embedded software and Python. Publish design guides, Requirement specification documents Follow ... - Jun 01
ASIC Digital Design, Staff Engineer
Synopsys
–
Sector 55, Uttar Pradesh, 201307, India
... - Must have experience in developing HVL (System Verilog or Vera or Specman) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage. - Must have strong HVL coding ... - May 25
R&D Engineering, Sr Staff Engineer
Synopsys
–
Sector 25A, Uttar Pradesh, 201301, India
... The person should have experience in C++, Verilog/VHDL and scripting. Problem solving and debugging for issues is key responsibility of the job. Customer interfacing and helping CAE with customer issues is required. Fast learner and effective ... - Jun 18
Applications Engineering, Sr Engineer
Synopsys
–
Sector 25A, Uttar Pradesh, 201301, India
... Strong HDL language support (Verilog, VHDL, System Verilog) Digital design fundamental and RTL coding understanding Good Debugging skills. Scripting – Perl, TCL, Make, Shell Scripting. Role - Static Product Engineer Solid fundamentals in Digital ... - Jun 07
ASIC Digital Design, Staff Engineer
Synopsys
–
Sector 55, Uttar Pradesh, 201307, India
... Requirements: Must have BSEE in EE with 4 to 8+ years of relevant experience or MSEE with 3 to 7+ years of relevant experience in the following areas: - Must have experience in developing HVL (System Verilog) based test environments, developing, and ... - May 25
R&D Engineering, Architect
Synopsys
–
Sector 25A, Uttar Pradesh, 201301, India
... Understanding of digital logic design, FPGA architecture, and hardware description language (like Verilog, System Verilog). EDA knowledge preferred, especially in partitioning, place-and-route, static timing analysis, synthesis or timing closure for ... - Jun 18
R&D Engineering, Staff Engineer
Synopsys
–
Sector 25A, Uttar Pradesh, 201301, India
... Experience 3-6 years’ experience in the verification domain Deep protocol insight in DDR4/5, DIMMs, HBM2/3 protocol Hands on experience of developing complex protocols verification components with SystemVerilog, Verilog and OVM/UVM methodology; ... - Jun 21
Applications Engineering, Staff Engineer
Synopsys
–
Sector 55, Uttar Pradesh, 201307, India
... The Engineer will also design and develop tests in VHDL/Verilog/System Verilog languages, resolving compile and functional/runtime issues for the zebu emulation platform. The candidate will benchmark various performance and compile time metrices of ... - Jun 18