| Job alert | Jobs 1 - 10 of 18 |
RTL Design Engineer
TekWissen ®
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Markham, ON, Canada
... RTL design and functional verification, synthesis, timing and formal verification Proficiency of Verilog or System Verilog Experience with multi-clock domain designs Experience in IP development Knowledge in video/display standards a plus. ... - Jun 02
Sr. Silicon Design Engineer
TekWissen ®
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Markham, ON, Canada
... Formality, CDC & Linting tools, Design Compiler/FX etc) Strong background in Verilog, System Verilog and/or scripting Strong analytical skills and attention to detail Excellent written and communication skills Experience with display/display related ... - Jun 02
RTL Design Engineer
TekWissen ®
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Markham, ON, Canada
... RTL design and functional verification, synthesis, timing and formal verification Proficiency of Verilog or System Verilog Experience with multi-clock domain designs Experience in IP development Knowledge in video/display standards a plus. ... - Jun 02
Senior ASIC Digital Design Engineer
Stathera, Inc.
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Toronto, ON, Canada
... Familiar with Verilog and Xcelium. Good knowledge of back-end synthesis tools Genus/Innn Shell, Perl, Python and TCL is a plus. Experience in defining synthesis constraints and STA. Scripting experience, and ability to apply good design quality ... - May 31
Sr. Silicon Design Engineer
TekWissen ®
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Markham, ON, Canada
... Formality, CDC & Linting tools, Design Compiler/FX etc) Strong background in Verilog, System Verilog and/or scripting Strong analytical skills and attention to detail Excellent written and communication skills Experience with display/display related ... - Jun 02
Staff DFT Engineer
Alphawave Semi
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Toronto, ON, Canada
... Good knowledge and understanding in Verilog/VHDL and SystemVerilog. Exposure to CAD and automation. Good exposure for using de-Perl techniques in creating generic codes. Knowledge of TCL and Python is a plus. Extensively experienced with main DFT ... - May 24
Senior Staff ASIC Implementation Engineer
Huntech USA LLC
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Markham, ON, Canada
... Expertise with Verilog/VHDL and ability to write clean, readable, synthesizable RTL. Exceptional understanding of ASIC/VLSI concepts, experience in logic synthesis using Synopsis and/or Cadence tools. STA. Ideally experience with High-speed/Low ... - May 16
ASIC Digital Design, Sr Engineer
Synopsys
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Britannia, ON, L4Z 2H7, Canada
... Main Responsibilities: Writing modular constrained-random Verilog and system-Verilog testbenches. Performing functional coverage, Assertion coverage, and code coverage; Creating and tracking testplans; Evaluating failure cases and running gate-level ... - Jun 06
Senior ASIC Verification Engineer - GPU
NVIDIA
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Downtown Toronto, ON, M5V 2T6, Canada
... with design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB) Expertise in System Verilog or similar HVL You display strong debugging and analytical skills Perl and C/C++ programming language experience ... - May 30
ASIC Digital Design, Principal Engineer
Synopsys
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Britannia, ON, L4Z 2H7, Canada
... and debug using Verilog and SystemVerilog Basic understanding of SerDes standards is an asset Scripting experience (Bash, Tcl, Python, Perl) is an asset Good organization and communication skills Inclusion and Diversity are important to us. ... - May 28