| Job alert | Jobs 1 - 10 of 283 |
Senior Design Verification Engineer
Mirafra Technologies
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India
... Experience Languages: System Verilog 3. Methodologies: OVM/UVM/VMM 4. Protocols: PCIE/NVMe/DDR/Ethernet 5. Processor/ARM Based SoC Verification experience 6. Candidate must have expertise in System Verilog. 7. Experience in ARM base SoC Verification ... - Jun 07
AMS Verification Engineer
NXP Semiconductors
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Noida, Uttar Pradesh, India
... to derive and understand the Analog-Digital boundaries and derive AMS test needs Work with designers to get the right schematic netlists or models needed for SoC AMS DV Modeling IPs as needed in Verilog/system Verilog/Verilog-a, Verilog ams etc. ... - May 27
ASIC Engineer, Design
Meta
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Bengaluru, Karnataka, India
... Responsibilities: ASIC Engineer, Design Responsibilities: Architecture exploration Micro-architecture development RTL development using Verilog, System Verilog and HLS Lint, CDC, Synthesis, & Power Optimization Soft and hard IP identification, ... - Jun 06
ASIC Engineer, Design
Meta
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Bengaluru, Karnataka, India
... Responsibilities: ASIC Engineer, Design Responsibilities: Architecture exploration Micro-architecture development RTL development using Verilog, System Verilog and HLS Lint, CDC, Synthesis, & Power Optimization Soft and hard IP identification, ... - May 31
FPGA Design Engineer
Mavenir
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Bengaluru, Karnataka, India
... Test on RFSOC based board Design documentation Job Requirements Very good knowledge on latest Xilinx/Intel FPGA architecture preferably Strong knowledge on digital design and excellent Verilog/VHDL coding skill Xilinx: Zynq/UltraScale/Ultrascale+); ... - Jun 12
Verification Lead
Mirafra Technologies
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Noida, Uttar Pradesh, India
... BE/MTECH with 7+ years of experience Languages: Verilog, System Verilog Methodology: UVM (preferred), OVM, VMM. Knowledge of scripting (Perl, C-shell) SVA will be a plus Good general verification experience with good academy results. Must-Have: SoC ... - Jun 03
Verification Lead
Mirafra Technologies
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India
... BE/MTECH with 7+ years of experience Languages: Verilog, System Verilog Methodology: UVM (preferred), OVM, VMM. Knowledge of scripting (Perl, C-shell) SVA will be a plus Good general verification experience with good academy results. Must-Have: SoC ... - Jun 03
SOC Verification Engineer
Wipro
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India
... • Good debug skills • System Verilog / UVM knowledge In addition Formal, Assertions, Coverage etc.. are positives. • Netlist simulation experience - Jun 07
RTL Verification Engineer: 5G Radio
Mavenir
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Bengaluru, Karnataka, India
... Proficiency in System Verilog and experience in UVM. Knowledge in ORAN protocol/DDR4, DMA, AXI interfaces. Familiarity in wireless communication concepts, signal processing concepts FFT/DUC/CFR/DPD/PRACH. Understanding in ORAN and 5G 3GPP standards. ... - Jun 13
AMS DV Engineer (1-2 Years)
Texas Instruments
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Bengaluru, Karnataka, India
... to derive and understand the Analog-Digital boundaries and derive AMS test needs Work with IP owners to get the right schematic netlists or models needed for SoC AMS DV Modeling IPs as needed in Verilog/system Verilog/Verilog-a, Verilog ams etc. ... - May 26