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Senior Design Verification Engineer

Tech Mahindra  –  India
... verification plan/verification methodology/flows from scratch Hands-on expertise with UMV (or similar) methodology, and Verilog/System Verilog (SV) Experience in constraint-random verification and/or transaction-based verification Experience in ... - Jun 05

Senior Design Verification Engineer

Tech Mahindra  –  India
... verification plan/verification methodology/flows from scratch Hands-on expertise with UMV (or similar) methodology, and Verilog/System Verilog (SV) Experience in constraint-random verification and/or transaction-based verification Experience in ... - Jun 05

Design Verification Lead

Tech Mahindra  –  India
... verification plan/verification methodology/flows from scratch Hands-on expertise with UMV (or similar) methodology, and Verilog/System Verilog (SV) Experience in constraint-random verification and/or transaction-based verification Experience in ... - Jun 05

ASIC Verification

Deep Vision Systems Pvt Ltd - Hyderabad  –  Hyderabad, Telangana, India
... verification environments from scratch Proficient at Verilog, UVM, EDA tools, scripting, automation, build, regression systems etc. Exposure to FPGA emulation platforms, silicon bringup, board debug BTech/MTech in EE/CS with any level of experience - May 25

Senior RTL Design Engineer

ACL Digital  –  India
... Should be proficient in Verilog. 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus. 3. Should have experience using ASIC ... - Jun 07

Senior Verification Engineer

NXP Semiconductors  –  Noida, Uttar Pradesh, India
... · Fluency in design & verification languages such as VHDL, Verilog, C and System Verilog. · Skilled in EDA test regression tools associated to Digital Front End Flow as vManager cadence tools. · Exposure to Low-power design and UPF methodology. · ... - Jun 16

RTL Design Engineer

L&T Technology Services  –  Bengaluru, Karnataka, India
... Experience/proficiency in RTL design(Verilog/VHDL) architecture implementation using (coding in) hardware description (RTL), IP Design, SoC Design and Integration. Should have hands on experience in all the Design aspects, should work independently. ... - Jun 13

Design Verification Lead

Tech Mahindra  –  India
... verification plan/verification methodology/flows from scratch Hands-on expertise with UMV (or similar) methodology, and Verilog/System Verilog (SV) Experience in constraint-random verification and/or transaction-based verification Experience in ... - May 26

ASIC Verification

Deep Vision Systems Pvt Ltd - Hyderabad  –  India
... verification environments from scratch Proficient at Verilog, UVM, EDA tools, scripting, automation, build, regression systems etc. Exposure to FPGA emulation platforms, silicon bringup, board debug BTech/MTech in EE/CS with any level of experience - May 25

Design Verification Engineer

Renesas Electronics  –  India
... Knowledge, Skills and Experience: The ideal candidate has an experience of 5+ years in state-of-the art verification methodologies related to the verification of SoCs · Fluent in System Verilog RTL coding and ASIC design methodology · System Verilog ... - Jun 18
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