| Job alert | Jobs 41 - 50 of 306 |
Analog Design Engineer
Aagama Consulting Services
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India
... Experience in .lib/Verilog view generation and validation. 6. Scripting knowledge is Plus. - Jun 05
IP Verification Engineer
Acesoft Labs India Pvt. Ltd.
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India
... • Proven track record of building test plan, UVM Environment and test benches • Experience with RTL debugging, scoreboard, assertions, functional coverage coding and code coverage analysis • Sound knowledge of Verilog and System Verilog languages • ... - May 31
ASIC Engineer, Implementation
Meta
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Bengaluru, Karnataka, India
... Experience Knowledge of RTL coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area Analysis and techniques for reducing power. Knowledge of Low power design. Experience ... - Jun 03
Python Automation Engineer
LTIMindtree
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India
... Must know Verilog, SystemVerilog. Knowledge in UVM is plus. Must be proficient in Python and make. Experience with Jenkins is a plus. Must have at least 2-3 years’ experience in automations using Python in ASIC/FPGA development or diag. Ideal ... - Jun 02
Hardware Design Developer
BrewApps LLC
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India
... Expertise in HDLs such as Verilog, SystemVerilog, VHDL, and SystemC. Expertise in scripting, front-end, and verification workflows, and integrations within the hardware design environment. Exceptional problem-solving, communication, and ... - Jun 01
Python Automation Engineer
LTIMindtree
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Bengaluru, Karnataka, India
... Must know Verilog, SystemVerilog. Knowledge in UVM is plus. Must be proficient in Python and make. Experience with Jenkins is a plus. Must have at least 2-3 years’ experience in automations using Python in ASIC/FPGA development or diag. Ideal ... - Jun 02
Memory IP Design - (MTPM/OTP/MRAM/SRAM/eFlash)
Globalfoundries
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Sadduguntepalya, Karnataka, 560029, India
... HSPICE, etc.) Experience in NVM Memory (MTPM/OTP/MRAM/SRAM/eFlash) designs Experience in timing characterization, Verilog is desirable General analog mixed-signal design concepts is desirable Circuit design, Reliability analysis, Statistical ... - Jun 13
Mixed Signal ASIC Design
VASBEAM Pvt Ltd
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Pune, Maharashtra, India
... Successful realization of more than 5 ASIC designs In depth knowledge of Cadence custom IC EDA tools Proficiency in system and behavioural modeling using MATLAB, System Verilog, Verilog-A/AMS. Experience with HDL languages Verilog and/or VHDL is ... - May 28
STA/Synthesis Engineer
Wipro
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India
... Fixing setup, Hold, TDRCs, Noise through ECOs Should have hands on tolls knowledge in: HDL’s: Verilog, VHDL EDA Tools: PTSI, Tempus, Tweaker, ICC2, Innovus, DCG/DCT Scripting Languages: Exposure to Perl, Shell, Tcl, Makefile Operating Systems: ... - Jun 07
Sr. Principal Digital Verification Engineer
Skyworks
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Bengaluru, Karnataka, India
... Job Requirements 15+ years (BSEE), 12+ years (MSEE), or 8+ years (PhD) of relevant industry experience Expertise in developing testbenches using System Verilog and UVM Experience using directed and constrained-random test methodologies, coverage ... - May 22