| Job alert | Jobs 21 - 30 of 355 |
Sr. Digital Verification Engineer
Skyworks
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Bengaluru, Karnataka, India
... Job Requirements 5+ years (BSEE), 3+ years (MSEE), or 0+ years (PhD) of relevant industry experience Expertise in developing testbenches using System Verilog and UVM Experience using directed and constrained-random test methodologies, coverage ... - May 22
Design Verification Python is must )
ACL Digital
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India
ACL Digital - An ALTEN Group Company is hiring Design Verification Engineer with python experience Experience : 1+ Years Job Location : Bangalore,India JD : Experience in UVM,System Verilog Python knowledge is must Excellent written and verbal ... - Jun 09
Emulation Engineer/Lead
Mirafra Technologies
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India
... Experience developing System Verilog based test content. Experience debugging failures using waveform viewers, log files and microcode trace dumps. Experience debugging software using debuggers and trace files. US Visa holders can also apply as I am ... - May 25
Senior Design Verification Engineer
ACL Digital
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Bengaluru, Karnataka, India
... verification Hands on experience with assembly, UVM, SV, C++ Experience in developing complex test bench/model in UVM, Verilog, System Verilog Hands on experience in developing test plans, coverage closure Ability to code readable, maintainable ... - May 30
AMS Verification
Cyient
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India
3 to 9 years experience in Analog Mixed Signal Verification • Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks • Good experience in Analog Mixed Signal verification simulation tools • Good experience in System Verilog, UVM ... - Jun 19
Field-Programmable Gate Arrays Engineer
Tonbo Imaging
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Bengaluru, Karnataka, India
... Strong RTL Programming skills in VHDL, Verilog. Tools : Lattice Diamond / Lattice Radiant. Good To Have Imaging processing /Video algorithms implementation in FPGA Good understanding of the following concepts: Multi Clock domain designs, ... - Jun 18
Lead Product Engineer RTL Design
Harman
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BTM Layout, Karnataka, 560076, India
... Experience with RTL coding using Verilog/VHDL/System Verilog. Experience in micro-architecture & designing cores and ASICs. Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc. Exposure in scripting (Pearl/Python/TCL ... - Jun 18
ASIC RTL Design Leads
Wipro
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India
... * Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog. * In depth knowledge on RTL quality checks (Lint, CDC). * Knowledge of synthesis and low power is a plus. * Good understanding of AMBA bus protocols ... - May 25
Senior Build and Release Methodology Engineer
NVIDIA
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Sadduguntepalya, Karnataka, 560029, India
... Background in RTL (Verilog), Verification (UVM, System Verilog) and C/C++ is a plus - Not must. Experience in synthesis and physical design is a plus - Not must. JR1973546 - Jun 11
Design Verification Engineer
TEKsystems
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Bengaluru, Karnataka, India
... Technical Skills: Proficient in Verilog for hardware design and verification. Strong experience with UVM for building reusable, scalable verification environments. Knowledge of UPF for low-power design verification. Proficient in Python for ... - Jun 18