| Job alert | Jobs 81 - 90 of 179 |
FPGA RTL Design Engineer
Intel
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Sadduguntepalya, Karnataka, 560029, India
... many teams worldwide involved in product development and delivery to customer Qualifications: Digital logic design experience in Verilog/SystemVerilog/VHDL Experience in developing unit level testbenches with Verilog/SystemVerilog Experience with ... - May 31
SOC Design Engineer
Intel
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Sadduguntepalya, Karnataka, 560029, India
... Skills: - Proficient in System Verilog/Verilog RTL coding. - Expertise in power-aware RTL coding/design. - Strong understanding of micro-architecture development and front-end flows such as Lint, CDC, low-power checks, etc. - Experience with ... - Jun 05
Principal Engineer - ASIC Digital Design
Mulya Technologies
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Bengaluru, Karnataka, India
... clock domain crossing etc Convert Architecture specification to Micro-architecture specification, implement logic functions in RTL using Verilog/System Verilog Test design using formal verification tools and functional verification environment. ... - Jun 20
SOC Design Engineer
Intel
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Sadduguntepalya, Karnataka, 560029, India
... Skills: - Proficient in System Verilog/Verilog RTL coding. - Expertise in power-aware RTL coding/design. - Ability to understand the micro-architecture of CPU subsystems and design associated component IPs, as well as define technical proposals. - ... - Jun 05
FPGA Principal Engineer
Thales
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Bengaluru, Karnataka, India
... Should have strong and hands on experience in VHDL and Verilog language. Strong experience in implementing FPGA code on the target hardware & testing with other system components and software. Strong experience in Synthesis, P&R, code constrain ... - Jun 20
RTL Design Engineer
Tessolve
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Bengaluru, Karnataka, India
... Technical Skillset Required: RTL Design using Verilog SOC IP Integration Interconnect Protocols: AHB, AXI, APB SOC Interfaces: GPIO, SPI, I2C, UART High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI Memory Interfaces: DDR or HBM I/O RTL ... - Jun 20
SOC Design Engineer
Intel
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Sadduguntepalya, Karnataka, 560029, India
... Skills: - Proficient in System Verilog/Verilog RTL coding. - Expertise in power-aware RTL coding/design. - Ability to understand the micro-architecture of CPU subsystems and design associated component IPs, as well as define technical proposals. - ... - Jun 07
ASIC Digital Design, Manager
Synopsys
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Sadduguntepalya, Karnataka, 560029, India
... Strong knowledge of Verilog/System Verilog language is needed. Hands-on experience with Synthesis, Timing Closure, DFT, Static Checks (CDC, RDC, LINT) Tools and Low Power Flows Hands-on experience in Assertion based Formal Property Verification is a ... - May 23
DESIGN VERIFICATION 9 TO BENGALURU & HYDERABAD
Capgemini
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Bengaluru, Karnataka, India
... Primary Skills: Verilog, SV, UVM/OVM, IP Verification, SoC Verification, scripting – Perl, Python, Shell, and Tcl. Secondary Skills: Test bench / model / VIP development, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHB/AXI/APB, ... - May 29
Physical Design and Machine Learning Engineer, Silicon
Google
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Bengaluru, Karnataka, India
... + Knowledge of computer architecture and Verilog/SystemVerilog. + Knowledge of circuit design, device physics, and sub-micron technology. + Knowledge of algorithms and data structures. Our computational challenges are so big, complex and unique we ... - Jun 11