| Job alert | Jobs 71 - 80 of 176 |
Design Verification Engineer
BITSILICA
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Bengaluru, Karnataka, India
... Experience building a Verification Environment from scratch using System-Verilog and methodologies like UVM / OVM. Experience in developing Test Plans and Test Cases Expertise in Coverage verification, Function coverage & Code coverage analysis ... - Jun 18
ACL Digital - Senior Design Verification Engineer - UVM/C++
ACL Digital
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Bengaluru, Karnataka, India
... level verification - Hands on experience with assembly, UVM, SV, C++ - Experience in developing complex test bench/model in UVM, Verilog, System Verilog - Hands on experience in developing test plans, coverage closure - Ability to code readable, ... - Jun 20
Senior Design Verification Engineer
7Rays Semiconductors India Private Limited
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Bengaluru, Karnataka, India
... Should have been part of End-to-End Verification Cycle Good knowledge of System Verilog, SV-OVM/SV-UVM Methodologies Experience with RTL concepts Knowledge of Perl/Python is Must Bachelor's Degree in Electrical, Electronics or Computer Engineering - Jun 18
FPGA Prototyping Engineer (Telecom Domain)
Ananant Systems Private Limited
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Bengaluru, Karnataka, India
... Implement and optimize FPGA designs using VHDL/Verilog or other hardware description languages. Perform simulation, verification, and debugging of FPGA designs. Conduct performance analysis and optimize FPGA implementations for speed, power, and ... - Jun 18
Sr Staff Verification Engineer
Synopsys Inc
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Bengaluru, Karnataka, India
... Ethernet Knowledge of System Level verification and validation, and digital design concepts Knowledge of languages such as Verilog, System Verilog, C/C++, and scripting languages- Perl/TCL/Shell, Python Knowledge of emulation and prototyping domains ... - Jun 18
FPGA Design Engineer
LeapFrog Semiconductor, Inc.
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Bengaluru, Karnataka, India
... work with architects to understand and influence the unit's architecture, plan and implement design changes in Verilog or SV, plan and implement verification environment in UVM, and execute the verification plan until all quality criteria are met ... - Jun 08
Senior/Lead DFT Engineer
Tessolve
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Bengaluru, Karnataka, India
... BIST, Analog/PHY test and post-silicon support Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent Knowledge of basic SoC architecture and HDL languages like Verilog to be able to work with logic design teams for timing fixes. ... - May 31
Principal Design Engineer
Cadence
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Bengaluru, Karnataka, India
... · RTL Design using Verilog is a must. · System Verilog experience and experience with UVM based environment usage / debugging is required. PCIe experience is highly desirable. We’re doing work that matters. Help us solve what others can’t. R46794 - Jun 13
FPGA RTL Design Engineer
Intel
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Sadduguntepalya, Karnataka, 560029, India
... many teams worldwide involved in product development and delivery to customer Qualifications: Digital logic design experience in Verilog/SystemVerilog/VHDL Experience in developing unit level testbenches with Verilog/SystemVerilog Experience with ... - May 31
SOC Design Engineer
Intel
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Sadduguntepalya, Karnataka, 560029, India
... Skills: - Proficient in System Verilog/Verilog RTL coding. - Expertise in power-aware RTL coding/design. - Strong understanding of micro-architecture development and front-end flows such as Lint, CDC, low-power checks, etc. - Experience with ... - Jun 05