| Job alert | Jobs 1 - 10 of 49 |
ASIC/RTL Engineer
Wipro
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Bengaluru, Karnataka, India
... Experience in post RTL checks — Lint, CDC, RDC Experience in RTL synthesis and static timing analysis Experience in working with technology dependent IPs (e.g., PLLs, IOs, Efuse etc) - May 18
Synthesis Engineer
Wipro
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Bengaluru, Karnataka, India
Title: PD(Synthesis) Engineer Description Full chip rollup, Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package design Full chip timing - Primetime constraints, clocks. Familiarity with low power design. UPF flow for defining power ... - May 25
PD - Frontend Synthesis
Wipro
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Bengaluru, Karnataka, India
... Fullchip rollup, Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package design Fullchip timing - PrimeTime constraints, clocks. Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains. ... - May 25
Software Engineer-DB
ZeOmega
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Bengaluru, Karnataka, India
... of Linked servers, CDC, Service Broker, Resource Governor, Replication, High Availability · Experience with tuning database and server for proper memory sizing, I/O distribution, physical space usage, load balancing and system resource allocation. ... - Jun 01
ASIC RTL Design Leads
Wipro
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Bengaluru, Karnataka, India
... * In depth knowledge on RTL quality checks (Lint, CDC). * Knowledge of synthesis and low power is a plus. * Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB). * Good understanding of timing concepts. * Knowledge of one or more of the ... - May 25
ASIC Engineer, Implementation
Meta
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Bengaluru, Karnataka, India
... We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications. ... - Jun 03
RTL Design Engineer
Wipro
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Bengaluru, Karnataka, India
... • Experience in post RTL checks — Lint, CDC, RDC • Experience in RTL synthesis and static timing analysis • Experience in working with technology dependent IPs (e.g., PLLs, IOs, Efuse etc) - May 16
ASIC Engineer, Design
Meta
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Bengaluru, Karnataka, India
... Responsibilities: ASIC Engineer, Design Responsibilities: Architecture exploration Micro-architecture development RTL development using Verilog, System Verilog and HLS Lint, CDC, Synthesis, & Power Optimization Soft and hard IP identification, ... - May 31
RTL ASIC Design Engineer
SA Technologies
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Bengaluru, Karnataka, India
... Experience in using the tools in ASIC development such as Lint and CDC are a must. Experience in Synthesis / Understanding of timing concepts is a plus. Good to have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. ... - May 24
RTL Design Engineer
Wipro
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Bengaluru, Karnataka, India
... In depth knowledge on RTL quality checks (Lint, CDC). Knowledge of synthesis and low power is a plus. Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB). Good understanding of timing concepts. Knowledge of one or more of the interface ... - May 25