| Job alert | Jobs 31 - 40 of 49 |
Processor Subsystem Architect
Intel
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Sadduguntepalya, Karnataka, 560029, India
... on advanced process nodes Must have been part of entire silicon cycle from architecture to tapeout and successful silicon bring-up, at least for 1 product Must be very strong on digital design including clocking, resets, power, CDC, RDC. ... - May 28
Senior Engineer- ASIC Design
Micron
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Bengaluru, Karnataka, India
... Skill Set Required: Strong fundamental knowledge of digital design, Verilog, and scripting language Experience with micro-architecture and synchronous and Asynchronous digital designs Working experience of Synthesis, STA, Lint & CDC Excellent ... - Jun 04
Staff SW QA Engr
Infinera
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Bengaluru, Karnataka, India
Your Key Responsibilities Would Include: Job Description: Develop detailed test plans and functional test strategies for Optical DWDM ROADM, CDC Muxponder, RAMAN/EDFA Amplifier and L1 Coherent Transponder/Switchponder applications Involve in testing ... - May 29
Design Manager Front End Design and Integration
L&T Semiconductor Technologies
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Bengaluru, Karnataka, India
... Experience with System Verilog and front-end tooling (simulation, waveform viewers, lint, CDC, RDC, etc.) is required, as well as highly efficient FE methodologies. Must have worked on complex, multi-core SoC’s with extensive interconnects and a ... - May 08
Application Specific Integrated Circuit Design Manager
Synopsys Inc
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Bengaluru, Karnataka, India
... Hands-on experience with Synthesis, Timing Closure, DFT, Static Checks (CDC, RDC, LINT) Tools and Low Power Flows Hands-on experience in Assertion based Formal Property Verification is a definite plus. Experience in Interface protocols like USB/PCIE ... - May 24
ASIC Digital Design, Staff Engineer
Synopsys
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Sadduguntepalya, Karnataka, 560029, India
... -- Integrate the RTL and drive the Design tasks to complete the Subsystem -- Sign-off on the front-end implementation flows like Synthesis timing closure using DC/Fusion Compiler, SpyGlass CDC/RDC checks, Low Power Architecture, Formality and others ... - May 30
Senior STA Engineer - ASIC Design
PEOPLE IMPACT
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Bengaluru, Karnataka, India
... Preferred Qualifications : - Experience with low-power design and clock domain crossing (CDC) analysis. - Familiarity with physical design concepts and methodologies. - Knowledge of statistical timing analysis and timing sign-off methodologies. ... - May 31
ASIC Digital Design, Staff Engineer
Synopsys
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Sadduguntepalya, Karnataka, 560029, India
... Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools Enhancing and maintaining existing SERDES PHY IPs supporting multiple protocols Creating, verifying and using Core-Kit views in Core Assembler flow. ... - May 28
ASIC Digital Design, Manager
Synopsys
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Sadduguntepalya, Karnataka, 560029, India
... Hands-on experience with Synthesis, Timing Closure, DFT, Static Checks (CDC, RDC, LINT) Tools and Low Power Flows Hands-on experience in Assertion based Formal Property Verification is a definite plus. Experience in Interface protocols like USB/PCIE ... - May 23
Digital Design Engineer
Analogdevices
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Bengaluru, Karnataka, India
... as caches, interconnect fabric, GIC, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, SPU) and their integration requirements Develop User Guides for RTL Integration, Synthesis, Lint/CDC waivers, DFT, PnR, Programming Sequence, characterization etc. ... - May 27