| Job alert | Jobs 21 - 30 of 56 |
Physical Design Engineer
L&T Technology Services
–
Bengaluru, Karnataka, India
... Good knowledge of all PnR activities like Floor-planning, Placement, CTS, Routing, Timing closure(STA), signoff checks like FEV, VCLP, EMIR and PV. Knowledge of industry standard EDA tools (Synopsys, Cadence, Mentor) Worked on DSM technologies, tsmc ... - Jun 13
Lead Static Timing Analysis & Sign-Off methodology Engineer
NXP Semiconductors
–
Mathikere, Karnataka, 560012, India
Summary: STA & Sign off Methodology Engineer with min 6 years of experience with expertise in STA tools who can support timing and Power analysis & closure while making sure a seamless use of Foundation IP solutions. Responsibilities: The STA and ... - Jun 10
Physical Design Engineer
UST
–
Bengaluru, Karnataka, India
... Hands-on experience in block/top level signoff STA, physical verification (DRC/LVS/ERC/antenna) checks and other reliability checks(IR/EM/Xtalk) Exposure in physical implementation of timing/functional ECO’s Good knowledge of VLSI process and device ... - May 19
PD Lead
Larsen & Toubro
–
Bengaluru, Karnataka, India
... If you have experience in #PnR, #STA, #Synthesis, and #PhysicalDesign, we encourage you to apply. This is an exciting opportunity to work in the #SemiconductorIndustry and be a part of our growing team. Don't miss out on this chance to further your ... - May 16
Sr.Physical Design Engineer
Tech Mahindra
–
Bengaluru, Karnataka, India
... Floorplanning, placement CTS, Routing • Design planning (partitioning, bump planning & Routing) • Very good understanding of STA • Very good Debugging skill • Understanding about Analog block integration • Low power design >>Signoff checks • LEC ( ... - May 23
Physical Design Engineer
BITSILICA
–
Bengaluru, Karnataka, India
Location: Bangalore/Hyderabad Experience: 5-12yrs Notice Period: Immediate to 15 Days Primary Skills : Physical Design, CTS, STA & Physical Verification · Experience on RTL2GDS Implementation i.e. Synthesis, Floor planning, Placement, CTS, Routing, ... - May 17
ASIC Static Timing Analysis Engineer
Google
–
Bengaluru, Karnataka, India
... + Experience with STA sign-off constraint authoring for full-chip level, tape-out sign-off requirements, checklists, and associated automation. + Experience in one or more static timing tools: PrimeTime, Tempus, Timing Closure, STA, Timing ECO using ... - Jun 11
Lead Physical Design Engineer
Cognitive Design Technology Pvt Ltd
–
Bengaluru, Karnataka, India
... shared NWELL methodology is highly desirable Experience in Cadence design flow is highly desirable/flat and hierarchical flow/STA timing signify/PV and PI signoff/ multi-bit flops/Retension flops Job Type: Full-time Benefits: Health insurance ... - Jun 05
Sr.RTL ASIC Design Engineer
Tessolve
–
Bengaluru, Karnataka, India
... Strong fundamental knowledge of digital design, Verilog, system Verilog and scripting languages Deep knowledge of IP/SoC design flows and methodologies (Lint, CDC, Synthesis/STA, Power) Excellent problem-solving skills. Team player with great ... - May 24
Senior Physical Design Engineer
7Rays Semiconductors India Private Limited
–
Bengaluru, Karnataka, India
... Significant knowledge and preferably hands on experience on SoC STA, Power, Physical Verification and other sign-off. Good problem-solving capabilities, proactive, hardworking with strong interpersonal skills. Bachelor's Degree in Electrical, ... - May 24