| Job alert | Jobs 21 - 30 of 49 |
ASIC RTL Engineer
Tech Mahindra
–
Bengaluru, Karnataka, India
... o Hands on experience in running Synopsys Fusion Compiler for Synthesis and Area and performance estimation o Perform RTL Lint check, Equivalence checking, CDC checking and support Static Timing Analysis, Static Power Checks, o Work closely with ... - May 12
Design Engineer
HTD Resources
–
Bengaluru, Karnataka, India
Position: Design Engineer Exp: 4-6 Years Location: Bangalore [Electronic City Phase II] Mode: 5 Days WFO NP: Only Immediate/15 Days Skills : ASIC, RTL, CDC, Lint Job Description: ·4 to 7 years of work experience in ASIC/IP Design. ·Experience in ... - May 29
RTL Principal Design Engineer
Cadence Design Systems
–
Bengaluru, Karnataka, India
... -Lead and also hands-on end-to-end ASIC design including RTL implementation and design processes of Lint/CDC/SDC definition/STA/Synthesis. -Collaborate with cross-functional teams of Architecture, Verification, Physical Design, and Mixed Signal ... - May 20
Technical Manager Chip Design Front End
Toshiba Software (India) Pvt. Ltd.
–
Bengaluru, Karnataka, India
... Key Responsibilities: RTL Design and DFT Integration, RTL Manipulation for DFT, RTL Coding Guidelines and Code Review Digital Verification Power Estimation and Optimization Clock Domain Crossing (CDC) EDA Tools for Front End Product Support for pre ... - May 18
System-on-Chip Design Engineer
7Rays Semiconductors India Private Limited
–
Bengaluru, Karnataka, India
... Experience in Lint/CDC checks Hand-on experience in Verilog HDL, System Verilog, C/C++ Drive one or more teams for their respective deliverables. Ensure the quality of deliverables and take necessary steps to improve the quality Excellent analytical ... - Jun 05
Informatica Admin
Mindpool Technologies
–
Bengaluru, Karnataka, India
... Install and configure Informatica Power Center and Power Exchange CDC components in UNIX environments with high availability (HA). Configuration of application services. (IS, Repository, Node etc.) Work experience in EBF installation. Install and ... - May 11
Lead CPU Design Engineer
Mulya Technologies
–
Bengaluru, Karnataka, India
... in RTL development in SystemVerilog/Verilog Well versed in industry standard RTL quality check methodologies such as lint and CDC checks Strong background in industry standards and protocols such as PCIe, Ethernet, CXL, AMBA AXI etc., Demonstrated ... - Jun 02
RTL Design Engineer
Eximietas Design
–
Bengaluru, Karnataka, India
... Designing for error cases and debug of IP Understanding of CDC logic Knowledge of lint rules and exceptions Design and use of block level simulations to bring up IP. Knowledge of AMBA buses and when to use them. Preferred: Experience leading small ... - May 17
IP RTL Design - RTL Architects & RTL Leads
Samsung Electronics
–
Bengaluru, Karnataka, India
... Must have knowledge in clock domain crossing (CDC), Linting, UPF, DFT and Multi-Voltage-Rule-Check analysis 7. Understanding on ASIC Synthesis, and static timing reports analysis, Formal checking, etc is a must. 8. Understanding and defining ... - May 08
RTL Design Lead
Texas Instruments
–
Bangalore Urban, Karnataka, India
... requirements, system level use-cases and pin mixing is fully comprehended Drive complete SoC integration, LEC, LINT checks and CDC/RDC analysis to ensure high quality deliverables Responsible for ensuring power intent of the SoC is understood and ... - May 23