Senior Design Verification Engineer

Position: Senior Design Verification Engineer

Location: Mountainview, California (Complete onsite)

What candidate will Be Doing:

Strong expertise along-with complex SoC/IP debug is must

At-least 5+ years of experience in System Verilog HVL and C/C++.

AMBA AXI bus along-with ARM or C based processor

Bi-frost/Processor based C and SV/UVM mix Verification. What we are looking for:

A bachelor's degree in electrical or computer engineering, accompanied by a minimum of 8 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline.

Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.

Verification closure with team

Make/Perl/Python

Ensure customer satisfaction.

Reporting to customer on daily or weekly progress effectively