US_West Desktop Engineer_L3

Description:

Possible 3 Month CTH No Fees Do Not Re-Post Confidential

Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO OPT OR CPT ALLOWED.

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Hiring Status: C2C/W2/1099QOpen for CTH (y/n):

Timeslots for Skype interview (provide Skype ID)

Due to additional onboarding requirements, a meet and greet is required for all new hires.

Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment.

If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to

Job Description: DFT Engineer

Location: SANTA CLARA (US:95051), CA

Qualification/Experience/Skills Required

• 10+ years of hands-on experience with DFT and test flow with commercial EDA tools (Synopsys, Mentor) for large and complex SoCs.

• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST, LBIST. Experience with Synopsys DFT Compiler, Tetramax and VCS is required.

• Experience with TestMaxDFT, SMS, TestMax Advisor tool suite is a plus.

• Experience in RTL simulation, synthesis, Linting, CDC checks, STA, DFT, quality metrics

• Hands-on expertise in writing System Verilog and VHDL

• Hands-on in Perl/TCL/Python/Unix scripting

• Excellent analytical, and problem-solving skills

• 8+ years' industry experience, Master's degree or equivalent in EE or Computer Engineering (CE)

Roles & Responsibilities

• Provide SoC (top) level constraints and partitions for RTL/Logic designers, floorplan & PD engineers, DFT requirements

• Perform top/block-level DFT insertion including scan compression, boundary scan, JTAG, IEEE 1500 wrapper, MBIST, LBIST, ATPG and pattern simulation.

• Verify DFT circuitry and interface with other blocks, debug timing simulation issues.

• Closely work with physical design team to generate and validate timing constraints.

• Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning.

• Be able to work independently and own the complete task from DFT specification to final pattern delivery for sub-system and/or SOC.

• Working closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power and area goals, functional and diagnostics test coverage

• Ability to lead/manage a team, with active technical interaction with engineering teams

Education: BSEE, in Electrical/Computer) OR (MSEE, in (Electrical/Computer)

Following skillsets are must:

- Experience with JTAG interface.

- Experience with TAP controller architecture

- Experience with Cadence tools for DFT

- Experience with at speed vectors, Boundary scan, Compression mode etc.

Job would require:

- Stitching multiple scan chains across different IP(mixed signal) and clock domains.

- Scan vectors generation, verification at different stages of the design.

- Validating scan coverage across design.

Additional Details

Global Grade : C

Named Job Posting? (if Yes - needs to be approved by SCSC) : No

Remote work possibility : No

Global Role Family : 60243 (P) Delivery Excellence

Global Technical Skills Family : 6269 (T) Office / Desktop Solutions

Local Role Name : DFT Engineer

Local Skills : Modasia Shobha (smodasia)

Languages Required: : English