Principal Digital ASIC Design Engineer

Location: Cambridge, MA (relocation paid)

Employment Type: Full-time, Direct Hire

Compensation & Benefits: Competitive base + top benefits + 10% 401(k)

The Role

Join a multidisciplinary team designing high-performance digital ASICs on advanced nodes.

You'll own the flow from architecture/RTL through synthesis, contribute to system-level design, and guide best practices across projects. This role blends deep technical execution with technical leadership and occasional proposal/business development support

What You'll Do

Architecture RTL Synthesis: Translate requirements into architectures; implement RTL; drive quality to tape-out.

Transistor-level design & simulation: Implement blocks at transistor level; run simulation (incl. extracted parasitics); guide floor-planning and physical layout partners.

System-level contribution: Evaluate hardware feasibility of complex algorithms; make performance/power/cost tradeoffs; optimize PPA.

DFT collaboration: Contribute to design-for-test strategy and integration.

Leadership & mentorship: Lead multi-disciplinary efforts, resolve ambiguity, document/teach best practices; support team leadership on complex programs.

Cross-functional delivery: Partner with verification, PD, packaging, firmware/software to land robust releases.

Biz-dev support: Contribute to proposals and customer engagements when needed. Education: BS in Electrical or Computer Engineering (or related); MS preferred.

Experience:

7-10+ years with BS or 5-10+ years with MS in ASIC hardware/front-end design.

Proven impact on complex chip architectures; history of successful tape-outs strongly desired.

Core Technical Skills:

RTL design: SystemVerilog / Verilog / VHDL.

EDA flows (Cadence or Synopsys): lint, simulation, synthesis.

Strong fundamentals in IC design, semiconductors, and computer architecture.

Ability to write clear design specifications and reviews. Core Competencies:

Independent problem-solving under unclear/incomplete requirements.

Excellent communication, documentation, organization, planning, and time-management.

Ability to lead multi-disciplinary teams and mentor engineers. Preferred / Nice to Have

Low-power design techniques; advanced CMOS nodes (<32nm).

Radiation-hardened electronics exposure.

Secure system architectures (e.g., cryptographic encoders/decoders, tagged processor architectures). Board-/System-Level Exposure:

Power integrity & power conditioning for digital PCB rails.

High-speed interfaces: DDR3/DDR4, PCIe, Gbit serial links.

Embedded/FPGA basics: microcontroller SW (C/C++/assembly) and FPGA firmware (VHDL/Verilog).

Understanding how circuit designs interface with SW/FW. Tools (additional): Siemens Designer & Layout, HyperLynx, ANSYS, SPICE, MATLAB.

Packaging: Experience with miniature electronic packaging (bare die, chip-scale); ability to influence custom packaging constraints/requirements.

Team leadership/management experience.

Security Requirement

Must be able to obtain and maintain a U.S. Government Security Clearance (requires U.S. citizenship). Why Join

Work on advanced digital IC designs across diverse applications.

High ownership at the Principal level; influence architecture, methodology, and team practices.

Relocation supported to Cambridge, MA; strong benefits including 10% 401(k)