Verification Engineer

Verification Engineer

Location: Chicago, IL - Onsite

Duration: 6 to 8 months

" Must have very good System Verilog/UVM experience in developing test benches

" Must have experience with developing test benches with RISC-V based SoC

" RISC-V processor verification is an added advantage

" Should have expertise developing scoreboards, monitors, and checkers

" Should have expertise in functional and code coverage

" Have experience in IP/SoC Verification

" Expertise in AMBA/AXI bus protocols

" Must have USB3.0 verification expertise

" Scripting Language (PERL/Python/Shell/Makefile)

" Must have good debugging and problem-solving skills

" Good to have GLS verification experience