Mixed-Signal Verification Engineer

In this role, you will be verifying RF/Mixed-Signal blocks and SOCs using SystemVerilog to create testbenches, checkers, models and tests. You will build and execute test plans to meet project schedule and metric requirements, including coverage metrics. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during aggressive schedules, we encourage you to apply.

BS with 3+ years relevant experience.

Solid experience in Mixed Signal Verification or Real Numbered Modeling of Mixed Signal Systems.

Modeling experience with RF/Mixed-Signal blocks and SOCs.

Expertise building Mixed-Signal testbenches, checkers and tests using System Verilog.

Experience in UVM methodology and HDL (System Verilog, Verilog) for verification.

Strong verification skills in problem solving, constrained random testing, and debugging.

Understanding of common analog/RF blocks and circuits.

Experience with signal processing using Python or Matlab.

Experience with Virtuoso Composer, ADE and HED.

Experience with Software Engineering and Python.

Ability to work well in a team and be productive under aggressive schedules to meet shared objectives and derive results.