Digital Design Engineers (RTL/P&R) - Senior Level

We're hiring: Digital Design Engineers – RTL / Physical Design (Mid & Senior)

Location: Aachen, Germany

If you have a background in digital circuit design - either in frontend RTL, backend physical design, or both - you might be a great fit.

We're working with a deep tech Semiconductor comapny who's looking for Digital Designers to develop cutting-edge digital and mixed-signal ICs on advanced process nodes like 22FDX and FinFET. Depending on your experience, there are opportunities to contribute at a technical or leadership level.

Key Responsibilities

Design and implement RTL for digital subsystems (e.g., DSP, control logic, interfaces)

Drive backend flows: synthesis, floorplanning, P&R, STA, and signoff

Interface with mixed-signal teams to ensure seamless integration

Develop testbenches and support silicon bring-up and validation

(Senior level) Lead architecture and mentor junior engineers

What You Bring

Strong RTL skills (SystemVerilog/VHDL) and scripting (Python, Tcl, etc.)

Solid experience with tools for synthesis, STA, and backend (Cadence, Synopsys, etc.)

Knowledge of low-power techniques, CDC, and hierarchical design

Experience in modern nodes (e.g., 22FDX, 16/12nm FinFET)

Understanding of mixed-signal integration and test concepts

Independent, detail-oriented, and solutions-driven mindset

Qualifications

Mid-Level: 3–5 years in digital IC design

Senior-Level: 6+ years, with track record of IP/block ownership

MSc or PhD in Electrical Engineering or related field

Interested to know more?

Apply here with your CV .

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