Senior FPGA Engineers

JD

• RTL FPGA design experience with Verilog, VHDL & System Verilog .

• experience in Xilinx FPGA Design.

• Design experience with Xilinx Vivado & ILA Hardware Debugger.

• Good understanding of FPGA architecture and MMCM clock structure.

• Experience with Ultrascale FPGA devices is a plus.

• Proficiency in clock gating and FPGA timing closer techniques.

EXP: 5+ Years

Location: Bangalore