TD Design Collateral Modeling Engineer

Company Description

Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful technology company with the spirit, agility, and entrepreneurial mindset of a start-up. In addition to the U.S. headquarters and other facilities in the U.S., the company has international presence in Asia, Europe, and the Americas. Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to be the #1 NAND memory company in the world. At Solidigm, we view problems as opportunities to define innovative solutions that hold the power to change the world and unleash the potential technological needs that the future holds. At Solidigm, we are One Team that fosters a diverse, equitable, and inclusive culture that embraces individual uniqueness and empowers us to bring our best selves to deliver excellence in support of Solidigm's vision and mission to be the go-to partner for optimized data storage solutions. You can be part of the takeoff of an innovative business that develops cutting-edge products, delivers strong business value for customers, provides an engaging workplace for its employees, and serves a greater impact on the world. This is a golden opportunity for the right applicant to join us and help design, build, and lead Solidigm. We want a diverse team of dedicated professionals who will not just be Solidigm team members but contribute to how we shape the future of the organization. We are seeking applicants who will grow and thrive in our culture; be customer inspired, trusting, innovative, team-oriented, inclusive, results driven, collaborative, passionate, and flexible.

Job Description

A TD Design Collateral Modeling Engineer is responsible for creating and refining models and data related to the design, including but not limited to CMOS Spice models, NAND array and interconnect RC models.

Key Responsibilities:

Model development: design and maintain modeling tiles on test chip and product scribes, perform electrical validations on silicon, generate device and interconnect RC models, calibrate models with corners based on fab process targets and variations.

Cross-functional collaboration: work closely with Device, Design, PI, and Process engineers to solve device and model related issues, meeting NAND performance target, passing technology qualifications. Qualifications

Required:

BS, MS, or PhD in a science or engineering field and minimum 5 years of experience in research or development environment for the relevant technical areas are required

Hands-on expertise in device modeling tools such as Verilog-A or similar simulation platforms

Strong understanding of semiconductor physics, particularly CMOS transistor operation and device scaling principles.

Strong communication and collaboration skills to work effectively with cross-functional teams. The candidate will need to be a collaboration role model, establishing strong technical and personal credibility, ensuring on-time project success through influencing and working with other organizations

Excellent statistical data analysis and problem-solving skills Preferred:

Hands-on expertise in electrical characterization techniques like IV curves, capacitance-voltage measurements, and device modeling.

Proficiency in TCAD simulation tools for device design and analysis

Experience with semiconductor fabrication processes

Demonstrated technical leadership and a track record of problem solving with creativity and out-of-box thinking

Working Conditions: This position is primarily office-based. Some international travel is expected.

Additional Information

The compensation range for this role is $136,750 - $252,010. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location.

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