FPGA Verification Engineer

The future of aerospace and defense starts here.

Ursa Major was founded to revolutionize how America and its allies access and apply high-performance propulsion, from hypersonics to solid rocket motors, satellite maneuvering and launch. We design and deliver propulsion and defense systems that solve the most urgent and critical national security demands.

Our products and technologies require an extraordinary team. A team that will mold tomorrow’s technologies while deploying today’s best. We are an intrinsically motivated team that has a passion for solving problems and empowering each other every day to develop our skills, knowing that there is always room for growth.

As an ASIC/FPGA Verification Engineer, you will be an integral part of the Avionics development team. You will architect, develop and execute test benches, verify requirements, collect functional and code coverage metrics, and prepare design review materials.

Responsibilities:

Architect and generate ASIC/FPGA test benches

Generate test cases and run simulations to verify the functionality of ASIC/FPGA code

Generate and perform testing on target hardware as part of post-silicon validation or integrated test environment (Hardware in the Loop)

Collect functional and code coverage metrics

Validate and verify ASIC/FPGA requirements

Help debug ASIC/FPGA design and/or test issues

Prepare materials for peer reviews and major program design reviews

Required Qualifications:

3+ years’ experience with SystemVerilog Universal Verification Methodology (UVM), Pyuvm or similar verification methodology

Experience with COCOTB and python-based HDL simulations

Experienced in running ASIC/FPGA simulations using QuestaSim, VCS, Riviero-Pro, or Verilator

Experienced in collecting ASIC/FPGA coverage metrics

Experienced in defining test plans, generating test cases and testbench components

Experienced in writing VHDL, Verilog or SystemVerilog code for ASIC/FPGA design

Experience in Python scripting, simulations and tool development

Preferred Experience:

ASIC/FPGA design experience

Digital circuit design experience

Experience with constrained random test benches

Experienced with assertion-based simulations

Experience validating DSP-centric designs

Experience running back-annotated ASIC/FPGA simulations

Colorado law requires us to tell you the base compensation range of this role, which is $110,000 - $150,000, determined by your education, experience, knowledge, skills, and abilities. The salary range for this role is intentionally wide as we are evaluating individuals based on their unique experience and abilities to fit our needs. Most importantly, we are excited to meet you, and see if you are a great fit for our team. What we can’t quantify for you are the exciting challenges, supportive team, and amazing culture we enjoy.

Benefits Include:

Unlimited PTO - Vacation, Sick, Personal, and Bereavement

Paid Parental and Adoptive Leave

Medical, Dental and Vision Insurance

Tax Advantage Accounts (HSA/FSA)

Employer Paid Short and Long Term Disability, Basic Life, AD&D

Additional Benefit Options Including Voluntary Life and Emergency Medical Transport

EAP Program

Retirement Savings Plan - Traditional 401(k) and a Roth 401(k)

Equity Grants in the Company

How To Apply

Interested candidates are encouraged to apply by clicking the “Apply Now” link at the top of the page. Usra Major will be accepting applications on a rolling basis until the position is closed.

NOTE: Research suggests that women and BIPOC individuals may self-select out of opportunities if they don't meet 100% of the job requirements. We encourage anyone who believes they have the skills and the drive necessary to succeed here to apply for this role.

US CITIZENSHIP, PERMANENT RESIDENCY, REFUGEE OR ASYLUM STATUS IS REQUIRED.

We’re an equal-opportunity employer. You will be considered for employment without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran, or disability status.

No outside recruiters, please.