RTL Design Engineer

Preferred Experience

Excellent track record in designing IP's, Subsystems involving CPUs, bus interconnects.

Working experience on Fetch Unit, MMU/IO-MMU, Load-Store, RISCV-Privilege Architecture, Advance Interrupt Architecture.

Worked with IP's or Subsystem involving CPUs like RISC-V, ARM or x86 is a big plus.

Knowledge of computer architecture, CPU designs like RISC-V, ARM & x86 ISA.

Well versed with understanding the systems using CPUs, security, safety.

Knowledge of In-Order, Out-of-Order execution, cache coherency, memory systems.

Understanding of Instruction fetch, Load & Store, FPU, ALU

Understanding of Debug and Trace infrastructure.

Design concepts configurability, scalability, automation.

Knowledge of AMBA bus protocols, DMA concepts.

Hands on experience with RTL coding using SV, Verilog, scripting language (Perl, Python, shell, TCL)

Good analytical and problem-solving skills.

Mentor junior engineers on the team Qualifications

Bachelor's/MS engineering in Electronics, Electrical, Computer Science or related fields.

6 to 15+ years of experience in ASIC design

Experienced with EDA tools, RTL coding, low power techniques, Lint, CDC and timing.

Knowledge of logic design principles along with timing, performance and power implications

bility to collaborate effectively with cross-functional teams

Excellent problem-solving and analytical skills

Strong attention to detail and ability to work in a fast-paced environment