About the job Candidate with 10+ years of experience in FPGA prototyping, who can work independently on the prototyping.
Candidate should be able to do modification independently in the verilog models and add/modify glue logic to fit into the FPGA system.
Should be able to run simulation in the FPGA test bench to ensure the basic QC checks met before handing of bit stream.
Needs to support the FW team in the debug.
Key Responsibilities FPGA bit file generation : Design/Modifying the verilog models and integrating the same in the SOC design to generate the FPGA bit files Debug issues independently with respect to the issues in FPGA synthesis..
Use/Modify the FPGA test bench to run the simulation for basic functional quality checks.
Debug Support: Work closely with the FW team, to provide the debug support.
Work with the design and DV team for issue debug and fix.
Documentation : Documenting clearly the step involved in the FPGA build and testbench set up.
Required Skills Strong knowledge of FPGA architecture, synthesis, place and route, timing closure, and related tools ( Vivaldo) Working experience on the HAPS boards Proficiency in Verilog to be able to modify the models to suit the platform Understanding of SoC architecture, AHB bus protocols, DDR controller, MIPI protocol, I2C protocol Experience debugging hardware and software issues.
Excellent communication and collaboration skills to work effectively with cross-functional teams.