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Phase-Locked Loop Design Engineer (PLL) - Visa Supported

Company:
European Tech Recruit
Location:
North Rhine-Westphalia, Germany
Posted:
July 18, 2025
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Description:

PLL Design Engineer

A fantastic opportunity for an experienced PLL Design Engineer to join an award-winning semiconductor company whose main product is a break-through and patented wide band width transceiver“ microchip for application in e.g. ultrafast 5G-A and 6G wireless infrastructure equipment and devices.

In this role, you will be responsible for the design, simulation, and verification of high-performance Phase-Locked Loops (PLLs) used in a variety of SoC and mixed-signal applications. You will work closely with system architects, digital designers, layout engineers, and verification teams to develop robust and silicon-proven PLL solutions for advanced process nodes such as 22FDX and other FinFET/FD-SOI processes.

Responsibilities

- Design and development of analog/mixed-signal PLL circuits, including VCOs, phase detectors, charge pumps, loop filters, and frequency dividers.

Perform schematic design, behavioral modeling, and transistor-level simulation (Spectre, HSPICE, Verilog A/AMS).

Optimize for low jitter, low power, and silicon area based on project requirements.

Collaborate with layout engineers to ensure layout-aware design integrity and performance.

Conduct design reviews and participate in silicon validation and debugging.

Provide documentation and support for integration into SoC environments

Your Profile

M.Sc. or Ph.D. in Electrical Engineering or related field.

Solid experience in analogue/mixed-signal IC design, particularly in PLLs, high-speed wireline SerDes, DDR or other high-speed applications.

Strong understanding of PLL theory, jitter analysis, and noise modeling .

Experience in designing op-amps, bandgaps, differential amplifiers, VCO, PLL, DLL .

Proficiency with Cadence design tools, Spectre, and behavioral modeling (Verilog -A, SystemVerilog-AMS).

Full-custom analog layout techniques and the ability to take a design and do all the layout extract verification and sign-off.

Experience with advanced CMOS process nodes. - Good communication skills and ability to work in a collaborative team environment .

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