STA Design Engineer (Static Timing Analysis)

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, communities, and the world.

Our mission is to build great products that accelerate next-generation computing experiences-building blocks for data centers, AI, PCs, gaming, and embedded systems.

Underpinning our mission is AMD's culture: we push innovation to solve important challenges, strive for execution excellence, and foster a culture of being direct, humble, collaborative, and inclusive of diverse perspectives.

THE ROLE: AMD is seeking an ASIC Design STA engineer to develop large SoCs with multiple physical blocks and over 300 clock domains.

Responsibilities include building and verifying timing constraints for complex SoC designs, requiring expertise in SDC, EDA tools, and TCL scripting.

Candidates should have extensive experience in SDC development and debugging, improving RTL quality metrics, and automating processes.

Familiarity with front-end (RTL) and back-end (Synthesis and P&R) processes is preferred.

THE PERSON: High-energy candidates with strong communication skills and organized work habits will excel.

Team orientation and goal focus are essential.

KEY RESPONSIBILITIES: Develop complex multi-mode/multi-corner timing constraints compatible with RTL and signoff.

Maintain RTL quality metrics in hierarchical designs and automate these processes.

Implement pre-route timing checks and QoR cleanup to prevent SDC issues and ensure quality handoff.

Collaborate with CAD teams on synthesis and STA workflows.

Combine SDC expertise, EDA tool proficiency, and TCL scripting skills in both EDA environments and Linux shell scripts.

Review and improve processes for early issue detection during design.

PREFERRED EXPERIENCE: Experience with EDA tools for RTL quality checks.

Building timing constraints for IPs, blocks, and full-chip in hierarchical flows.

Analyzing timing reports and resolving related issues.

Ability to multitask and learn new tools and methodologies.

Experience with Synopsys Design Compiler, PrimeTime, Spyglass, Fishtail, etc.

Developing complex TCL scripts in Synopsys tools.

Creating custom TCL QC and QoR checks.

Strong analytical and problem-solving skills.

ACADEMIC CREDENTIALS: Bachelor's or Master's degree in Electrical or Computer Engineering.

LOCATION: San Jose, CA #LI-HYBRID #LI-AP1 Benefits are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based services.

We are an equal opportunity employer and consider all applicants without regard to legally protected characteristics.

We encourage all qualified candidates to apply and will provide accommodations during the recruitment process.

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