ATE Test Engineer - HP

Job Title: Senior ATE Test Engineer (HP 93K)

Location: Aliso Viejo, CA (Onsite)

Job Type: Contract

Industry: Semiconductor / IC Test Engineering

Experience Level: Senior (7+ years)

Job Description:

We are seeking a highly experienced Senior ATE Test Engineer with deep expertise in Advantest/HP 93000 (93K) platform to join our growing semiconductor test team. This role is ideal for a hands-on engineer who thrives in a fast-paced environment and possesses a solid understanding of automated test development, debug, and production support across a range of analog, digital, and mixed-signal devices.

Key Responsibilities:

Develop, debug, and validate ATE test programs for new silicon products using HP 93K (Advantest V93000) platform

Create and execute test plans for engineering validation and high-volume production

Collaborate with design, product, and packaging teams to define test requirements and DFT strategies

Optimize test program performance for throughput, memory usage, and test coverage

Support wafer sort and final test during NPI and volume ramp-up

Analyze yield data and perform failure analysis to drive continuous quality improvement

Work with overseas manufacturing partners to support test transfers and high-volume production

Maintain detailed documentation and provide knowledge transfer to junior engineers as needed

Required Qualifications:

Bachelor’s or Master’s degree in Electrical Engineering or related field

7+ years of direct experience in ATE development, with strong proficiency on the HP/Advantest 93000 (93K) platform

Strong knowledge of digital and mixed-signal test methodologies, test hardware design, and ATE interface board development

Experience with test development in C/C++, PERL, Python, or equivalent scripting languages

Deep understanding of device characterization, yield improvement, and production test optimization

Hands-on experience with lab equipment such as oscilloscopes, logic analyzers, power supplies, and source measurement units (SMUs)

Familiarity with device datasheets, test specification documents, and datasheet limit extraction

Preferred Skills:

Experience with other ATE platforms (e.g., Teradyne UltraFLEX, ETS, or Verigy)

Background in RF, analog, or power management IC testing

Knowledge of Design for Test (DFT) and scan test methodologies

Experience working with offshore test houses and contract manufacturers

Exposure to yield analysis tools (e.g., Galaxy, JMP) and test data management systems

Proven ability to lead and mentor junior engineers

Compensation: $40 - $80 per hour depending on experience