Resolution Enhancement Techniques (RET) Process Development Engr
Description:
About Us: Texas Instruments is a leading innovator in advanced analog/mixed-signal devices.
We are committed to pushing the boundaries of technology and delivering cutting-edge solutions to our global customers.
Join our dynamic team and contribute to the next generation of 28nm/22nm node Job Description: We are seeking a highly skilled and motivated Design Retargeting Engineer to join our RET(Resolution Enhancement Team) in ATD.
In this role, you will be responsible for translating customer design intent into manufacturable layouts by applying advanced retargeting techniques.
You will work at the intersection of design and process, ensuring that physical layouts are optimized for yield, performance, and manufacturability across various technology nodes.
Responsibilities: * Develop and implement design retargeting strategies to bridge the gap between design intent and process capabilities.
* Collaborate with OPC, lithography, and process integration teams to ensure accurate pattern transfer and high-yield manufacturing.
* Analyze and modify layout geometries to improve printability and process window robustness.
* Work with EDA tools to automate retargeting flows and integrate them into the tape-out pipeline.
* Support customer design enablement by providing feedback on layout constraints and manufacturability guidelines.
* Perform data analysis using CD metrology, SEM review, and simulation results to refine retargeting rules.
* Contribute to the development of design rules and patterning strategies for advanced nodes (e.g., 28nm, 22nm). * Mentor junior engineers and contribute to knowledge sharing within the team.
Qualifications: * Master's in Electrical Engineering, Physics, Materials Science, or a related field.
* 5+ years of experience in design retargeting, OPC, or physical design in a semiconductor or EDA environment.
* Strong understanding of optical lithography principles, RET (e.g., OPC, SRA, assist features), and mask technology.
* Hands-on experience with industry-standard OPC software tools (e.g., Synopsis Sentaurus Lithography, Mentor Calibre, ASML Brion). * Proficiency in scripting with any scripting languages * Familiarity with layout editing and verification tools (e.g., Calibre, Virtuoso, ICC2). * Understanding of lithography, patterning, and process integration challenges in advanced nodes.
* Familiarity with 28nm/22nm process limitations and lithographic constraints.
Preferred Qualifications: * PhD in Electrical Engineering, Physics, Materials Science, or a related field.
* Experience with advanced technology nodes (e.g., 45nm, 28nm, 22nm, and 20nm ). * Solid knowledge of semiconductor device physics and fabrication processes.
* Experience in analog layout interaction with lithography and OPC flows.
* Experience with statistical data analysis and yield improvement methodologies.
* Strong analytical and problem-solving skills.
* Ability to work effectively in a cross-functional team environment.
* Excellent problem-solving, analytical, and communication skills.
* Knowledge of design rule checking (DRC) and layout versus schematic (LVS). * Knowledge of Design Technology Co-Optimization (DTCO) * Exposure to machine learning or data-driven approaches for layout optimization.
Qualifications: * Master's in Electrical Engineering, Physics, Materials Science, or a related field.
* 5+ years of experience in design retargeting, OPC, or physical design in a semiconductor or EDA environment.
* Strong understanding of optical lithography principles, RET (e.g., OPC, SRA, assist features), and mask technology.
* Hands-on experience with industry-standard OPC software tools (e.g., Synopsis Sentaurus Lithography, Mentor Calibre, ASML Brion). * Proficiency in scripting with any scripting languages * Familiarity with layout editing and verification tools (e.g., Calibre, Virtuoso, ICC2). * Understanding of lithography, patterning, and process integration challenges in advanced nodes.
* Familiarity with 28nm/22nm process limitations and lithographic constraints.
Preferred Qualifications: * PhD in Electrical Engineering, Physics, Materials Science, or a related field.
* Experience with advanced technology nodes (e.g., 45nm, 28nm, 22nm, and 20nm ). * Solid knowledge of semiconductor device physics and fabrication processes.
* Experience in analog layout interaction with lithography and OPC flows.
* Experience with statistical data analysis and yield improvement methodologies.
* Strong analytical and problem-solving skills.
* Ability to work effectively in a cross-functional team environment.
* Excellent problem-solving, analytical, and communication skills.
* Knowledge of design rule checking (DRC) and layout versus schematic (LVS). * Knowledge of Design Technology Co-Optimization (DTCO) * Exposure to machine learning or data-driven approaches for layout optimization.