Senior SoC/ASIC Physical Design Engineer

About Xcelerium:

Xceleirum is a fabless semiconductor company developing advanced edge processors that bring AI processing to high-bandwidth sensors and wireless devices, unlocking hidden insights from every RF signal.

Working at Xcelerium will provide an opportunity to work on a complex development from the ground up and become familiar with cutting edge technologies such as the wireless signal processing, computer vision, sensor fusion, machine learning and inner workings of frameworks such as TensorFlow, PyTorch, OpenCL and OpenGL, etc. In addition, the application domains will be 5G, UAVs/Drone, Robots, and Autonomous Vehicles which provide enormous scope for growth and making an impact.

About the Job

As a Senior SoC/ASIC Physical design Engineer, you will work on developing and implementing flow and methodologies and the physical implementation to optimize the design for performance, power efficiency, and area.

Responsibilities

Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)

Develop/improve physical design methodologies and automation scripts for various implementation steps

Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs

Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution

Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

Qualifications

Bachelor’s degree in electrical engineering, computer engineering or computer science

10+ years of ASIC and/or physical design flow development experience

Experience with ASIC physical design, physical design flows and methodologies (i.e., synthesis, place and route, STA, formal verification, CDC or power analysis using industry standard tools).

Scripting experience with Python, Tcl, or Perl

Experience in extraction of design parameters, QOR metrics, analyzing trends, voltage scaling (SVS, DVFS), and SRAM split rail implementation.

Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows

Strong experience with Synopsys EDA tools including understanding of their capabilities and underlying algorithms

Strong knowledge of deep sub-micron FinFET and CMOS solid state physics

Strong knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries

Deep understanding of CMOS power dissipation in deep submicron processes leakage/dynamic

Familiar with CMOS analog circuit and physical design

Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows

Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)

Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

Compensation And Benefits

We provide competitive compensation package