Post Silicon Validation Engineer

Position: Post Silicon Validation Engineer

Location: San Diego, CA

Duration: Contract

Job Description:

Validate DDR interfaces by referencing JEDEC specifications and analyzing bus-level transactions.

Perform Regression and PVT (Process, Voltage, Temperature) testing across silicon and emulation environments.

Support Emulation Build Validation, including configuration, execution, and result analysis.

Read and interpret C code to understand test frameworks and code flow.

Modify and iterate C-based test cases to enable thorough validation coverage.

Identify, isolate, and debug hardware/firmware issues using tools like JTAG and logic analyzers.

Collaborate with cross-functional teams for bug reproduction and root cause analysis.

Review test data and maintain structured documentation of results.

Contribute to post-silicon bring-up and subsystem-level validation.

Support automation and optimization of validation processes and infrastructure.