System Verilog UVM Design Verification Test Engineer

Hybrid Job Description: The project relates to the design and verification of a custom controller for analog components.

The controller has interfaces such as SPI, Ethernet and AXI to drive the internal components and send data.

Responsibilities: UVM/python test development for driving VIPs and other stimulus drivers Generation of test components such as monitors, scoreboards and python models Coverage closure and GLS bringup and testing Experience: 6+ years of experience with verification methodologies and languages such as UVM and SystemVerilog.

Experience developing and maintaining verification testbenches, test cases, and test environments.

Experience in all aspects of verification life cycle, specifically, SDF and GLS simulations Experience in ethernet and SPI required UVM/System Verilog experience 5+ years High proficiency in python Experience in assertions and formal verification preferred Experience in ethernet, SPI, AXI, JTAG preferred Experience in analog and real number modeling preferred Skills: UVM/System Verilog Design Verification Ethernet, SPI, AXI, JTAG SDF and GLS simulations Python Education: Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

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