Silicon Verification Manager - AI Accelerators

Reality Labs (RL) focuses on delivering Meta's vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon.

Reality Labs Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body.

Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day.

We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.

As a Design Verification Manager at Meta Reality Labs, you will work with and support a world-class group of researchers and engineers, and use your digital design verification and pre/post-Silicon validation skills/knowledge to drive strategy, planning and prioritization for testing infrastructure, verification and validation of machine learning Hardware IP.

You will partner with cross-functional teams to develop and optimize state of the art machine learning Hardware accelerators, Software stacks and workloads.

You will work closely with ML researchers, architects and designers in creating verification strategies, methodologies, and cross-functional verification plans for multiple state of the art IPs.

Responsibilities:

Silicon Verification Manager - AI Accelerators Responsibilities:

Support design verification team members’ skills development, career and personal growth, task prioritization and ownership

Work with cross-functional partner teams defining and improving SW-HW verification methodologies and strategies for Machine learning accelerator IP

Define and track project milestones and detailed plans for module- and top-level functional, power, and performance verification

Support implementation of scalable test benches including checkers, reference models, and assertions, directed and random tests

Track and report functional coverage metrics, power and performance metrics, and bugs encountered and fixed

Support SW-HW co-design, development of SW unit tests and/or custom kernels

Support post silicon bring-up and debug activities

Qualification and experience:

Minimum Qualifications:

4+ years supporting design verification teams, driving strategy/planning and cross-functional partner collaboration on low power/high performance IP/SOC projects

2+ years of Management or Technical leadership experience

6+ years of System Verilog UVM DV experience

Knowledge with assertions (SVA) or others

Knowledge of digital ASIC design flows, project management and milestones

Knowledge of X-propagation, UPF-power aware, Gate-level simulations

Experience with at least 1 procedural programming language (C, C++, Python etc)

Results oriented, self-motivated, proactive with demonstrated critical thinking

MS EE/CS or equivalent experience

Preferred:

Preferred Qualifications:

Experience in Machine Learning IPs Silicon development

Exposure to other verification methodologies (formal, co-simulation, etc)

FPGA/Emulation prototyping and debug experience

Experience with SW-HW co-design, firmware/HW interaction testing

Experience with AI algorithms, DSP coding and optimization

Experience to collaborate and/or lead in a team environment

PhD in Electrical Engineering or Computer Science or equivalent experience