ASIC Design Verification Engineer

Responsibilities :

• Work with RTL designers and software engineers to ensure a high quality design that works first silicon.

• Develop detailed test and coverage plans based on the micro-architecture.

• Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage.

• Write tests, manage regressions, gather coverage, and debug test failures.

Required Skills and Qualifications:

• Great debugging and problem solving skills.

• Deep knowledge of System Verilog testbench language, DPI, and UVM.

• Excellent programming skills and knowledge of software engineering practices including object-oriented design.

• Experience developing scalable and portable testbenches and components.

• Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations.

• Proficient in a scripting language such as Python or Perl.

• 5 years of Design Verification experience.