Memory PHY RTL Design Engineer

Job Description

We are looking for Memory PHY RTL Design Engineer for our client in Boxborough, MA

Job Title: Memory PHY RTL Design Engineer

Job Location: Boxborough, MA

Job Type: Contract

Job Description:

Pay Range: $55hr - $70hr

Responsibilities:

RTL design for memory I/O.

PHY Digital Architecture development from pathfinding, coding, verification to physical implementation.

PHY link layer design, implementation & verification with Analog and System architect.

PHY Analog/Digital co-design.

Digital design and RTL coding.

Timing Synthesis & Drive Physical implementation.

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.

Build the unit tests.

Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues.

Preferred Experience:

Digital design engineering experience.

Proficient in debugging firmware and RTL code using simulation tools.

Proficient in using UVM testbenches and working in Linux and Windows environments.

Experienced with Verilog, System Verilog, C, and C++.

Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus.

Knowledge of clocking architectures, synchronization, and CDC methodology.

SERDES, DDR, Memory Controller, or MAC Design experience is preferred.

Strong understanding of computer organization/architecture.

Mixed signal RTL experience is a plus.

Academic Credentials:

Bachelors or Masters degree in computer engineering/Electrical Engineering.Company Description

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